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Thermal-Aware Testing of Digital VLSI Circuits and Systems [Kõva köide]

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(Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, West Bengal, India)
  • Formaat: Hardback, 118 pages, kõrgus x laius: 216x138 mm, kaal: 300 g, 10 Illustrations, black and white
  • Ilmumisaeg: 25-Apr-2018
  • Kirjastus: CRC Press Inc
  • ISBN-10: 0815378823
  • ISBN-13: 9780815378822
Teised raamatud teemal:
Thermal-Aware Testing of Digital VLSI Circuits and SystemsSuurem pilt
  • Formaat: Hardback, 118 pages, kõrgus x laius: 216x138 mm, kaal: 300 g, 10 Illustrations, black and white
  • Ilmumisaeg: 25-Apr-2018
  • Kirjastus: CRC Press Inc
  • ISBN-10: 0815378823
  • ISBN-13: 9780815378822
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780815378822.html
Märksõnad:
This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system level

Describes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniques

This book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips
List of Abbreviations
xi
Preface xiii
Acknowledgments xvii
Author xix
Chapter 1 VLSI Testing: An Introduction
1(24)
1.1 Testing In The VLSI Design Process
2(3)
1.2 Fault Models
5(3)
1.2.1 Stuck-at Fault Model
6(1)
1.2.2 Transistor Fault Model
6(1)
1.2.3 Bridging Fault Model
7(1)
1.2.4 Delay Fault Model
7(1)
1.3 Test Generation
8(2)
1.3.1 D Algorithm
8(2)
1.4 Design For Testability (DFT)
10(6)
1.4.1 Scan Design---A Structured DFT Approach
11(3)
1.4.2 Logic Built-in Self Test (BIST)
14(2)
1.5 Power Dissipation During Testing
16(4)
1.5.1 Power Concerns During Testing
17(3)
1.6 Effects Of High Temperature
20(1)
1.7 Thermal Model
21(3)
1.8 Summary
24(1)
References
24(1)
Chapter 2 Circuit-Level Testing
25(28)
2.1 Introduction
25(2)
2.2 Test-Vector Reordering
27(12)
2.2.1 Hamming Distance-Based Reordering
28(3)
2.2.2 Particle Swarm Optimization-Based Reordering
31(8)
2.3 Don't Care Filling
39(5)
2.3.1 Power and Thermal Estimation
41(1)
2.3.2 Flip-Select Filling
42(2)
2.4 Scan-Cell Optimization
44(3)
2.5 Built-In Self Test
47(3)
2.5.1 PSO-based Low Temperature LT-RTPG Design
49(1)
2.6 Summary
50(3)
References
51(2)
Chapter 3 Test-Data Compression
53(18)
3.1 Introduction
53(2)
3.2 Dictionary-Based Test Data Compression
55(1)
3.3 Dictionary Construction Using Clique Partitioning
56(3)
3.4 Peak Temperature And Compression Trade-Off
59(4)
3.5 Temperature Reduction Without Sacrificing Compression
63(6)
3.6 Summary
69(2)
References
69(2)
Chapter 4 System-on-Chip Testing
71(24)
4.1 Introduction
71(1)
4.2 SOC Test Problem
72(2)
4.3 Superposition Principle-Based Thermal Model
74(4)
4.4 Test Scheduling Strategy
78(12)
4.4.1 Phase I
79(6)
4.4.2 Phase II
85(1)
4.4.2.1 PSO Formulation
85(1)
4.4.2.2 Particle Fitness Calculation
86(4)
4.5 Experimental Results
90(2)
4.6 Summary
92(3)
References
94(1)
Chapter 5 Network-on-Chip Testing
95(16)
5.1 Introduction
95(3)
5.2 Problem Statement
98(1)
5.3 Test Time Of NOC
99(1)
5.4 Peak Temperature Of NOC
100(1)
5.5 PSO Formulation For Preemptive Test Scheduling
101(2)
5.6 Augmentation To The Basic PSO
103(1)
5.7 Overall Algorithm
104(2)
5.8 Experimental Results
106(1)
5.8.1 Effect of Augmentation to the Basic PSO
106(1)
5.8.2 Preemptive vs. Non-preemptive Scheduling
107(1)
5.8.3 Thermal-Aware Test Scheduling Results
107(1)
5.9 Summary
107(4)
References
109(2)
Index 111
Santanu Chattopadhyay received BE degree in Computer Science and Technology from Calcutta University (BE College), Kolkata, India, in 1990. In 1992 and 1996 he received M.Tech in Computer and Information Technology and PhD in Computer Science and Engineering, respectively, both from the Indian Institute of Technology, Kharagpur, India. He is currently a professor in the Electronics and Electrical Communication Engineering department, Indian Institute of Technology, Kharagpur. His research interests include low-power digital circuit design and test, System-on-Chip testing, Network-on-Chip design and test, logic encryption. He has more than hundred publications in refereed international journals and conferences. He is a co-author of the book Additive Cellular Automata Theory and Applications published by the IEEE Computer Society Press. He has also co-authored the book titled Network-on-Chip The Next Generation of System-on-Chip Integration published by the CRC Press. He has written a number of text books, such as, Compiler Design, System Software, Embedded System Design, all published by the PHI Learning, India. He is a senior member of the IEEE and also one of the regional editors (Asia region) of the IET Circuits, Devices and Systems journal.