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Through Silicon Vias: Materials, Models, Design, and Performance [Kõva köide]

, , (Indian Institute of Technology-Roorkee, India),
  • Formaat: Hardback, 216 pages, kõrgus x laius: 234x156 mm, kaal: 566 g, 23 Tables, black and white; 28 Illustrations, color; 108 Illustrations, black and white
  • Ilmumisaeg: 26-Aug-2016
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1498745520
  • ISBN-13: 9781498745529
Teised raamatud teemal:
Through Silicon Vias: Materials, Models, Design, and PerformanceSuurem pilt
  • Formaat: Hardback, 216 pages, kõrgus x laius: 234x156 mm, kaal: 566 g, 23 Tables, black and white; 28 Illustrations, color; 108 Illustrations, black and white
  • Ilmumisaeg: 26-Aug-2016
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1498745520
  • ISBN-13: 9781498745529
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781498745529.html
Märksõnad:

Recent advances in semiconductor technology offer vertical interconnect access (via) that extend through silicon, popularly known as through silicon via (TSV). This book provides a comprehensive review of the theory behind TSVs while covering most recent advancements in materials, models and designs. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for Cu, carbon nanotube (CNT) and graphene nanoribbon (GNR) based TSVs are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR based TSVs are also discussed.

Preface xi
Authors xiii
1 Three-Dimensional Technology and Packaging Techniques
1(22)
1.1 Introduction
1(4)
1.1.1 Conventional Packaging Techniques
1(3)
1.1.2 Limitations
4(1)
1.1.3 Recent Advances in Packaging Technology
4(1)
1.2 Packaging Techniques of Future ICs
5(9)
1.2.1 Silicon Interposer Technology
7(1)
1.2.2 Through Silicon Vias
8(1)
1.2.3 Hybrid Packaging Technique
9(1)
1.2.4 Silicon-Less Interconnect Technology
10(1)
1.2.5 Comparison of Different Packaging Techniques
11(3)
1.3 3D Integrated Architectures
14(3)
1.3.1 3D Integrated Microprocessor
14(1)
1.3.2 SRAM Array Integration
14(1)
1.3.3 Network-on-Chip Architecture
15(1)
1.3.4 Wireless Sensor Network Architecture
16(1)
1.4 Summary
17(6)
Multiple Choice Questions
18(1)
Short Questions
19(1)
Long Questions
20(1)
References
20(3)
2 Through Silicon Vias: Materials, Properties, and Fabrication
23(52)
2.1 Introduction
23(1)
2.2 History of Graphene
24(1)
2.3 Carbon Nanotubes
25(12)
2.3.1 Basic Structure of CNT
26(1)
2.3.1.1 Basic Structure of Single-Walled CNT
26(3)
2.3.1.2 Basic Structure of Multiwalled CNT
29(2)
2.3.2 Semiconducting and Metallic CNTs
31(2)
2.3.3 Properties and Characteristics
33(1)
2.3.3.1 Strength and Elasticity
33(1)
2.3.3.2 Thermal Conductivity and Expansion
33(1)
2.3.3.3 Field Emission
34(1)
2.3.3.4 Aspect Ratio
34(1)
2.3.3.5 Absorbent
34(1)
2.3.3.6 Conductivity
34(3)
2.4 Graphene Nanoribbons
37(5)
2.4.1 Basic Structure of GNR
37(2)
2.4.2 Semiconducting and Metallic GNRs
39(1)
2.4.3 Properties and Characteristics
40(1)
2.4.3.1 MFP of GNR
40(2)
2.5 Properties of TSVs
42(15)
2.5.1 Electrical Properties
42(3)
2.5.2 Thermal Transport
45(3)
2.5.3 Mechanical Performance
48(6)
2.5.4 Thermomechanical Properties
54(3)
2.6 Fabrication of TSVs
57(6)
2.6.1 Via-First TSV
58(1)
2.6.2 Via-Middle TSV
58(1)
2.6.3 Via-Last TSV
59(1)
2.6.4 Etching
59(1)
2.6.5 Deposition of Oxide
60(1)
2.6.6 Barrier Layer or Seed Layer
60(1)
2.6.7 Via Filling/Plating
61(1)
2.6.8 Chemical Mechanical Polishing
62(1)
2.6.9 Wafer Thinning
62(1)
2.7 Challenges for TSV Implementation
63(3)
2.7.1 Cost
63(1)
2.7.2 Design
64(1)
2.7.3 Testing
65(1)
2.7.4 Warpage Occurrence
65(1)
2.7.5 Manufacturing
66(1)
2.8 Summary
66(9)
Multiple Choice Questions
67(2)
Short Questions
69(1)
Long Questions
70(1)
References
70(5)
3 Copper-Based Through Silicon Vias
75(22)
3.1 Introduction
75(1)
3.2 Physical Configuration
76(2)
3.3 Modeling of Cu-Based TSVs
78(8)
3.3.1 Scalable Electrical Equivalent Model of Coupled TSVs with Bumps
79(3)
3.3.2 Modeling of Multicoupled TSVs
82(1)
3.3.3 Modeling of Coupled TSVs with MES Ground Structure
83(1)
3.3.4 Modeling of TSVs with Ohmic Contact in Silicon Interposer
83(3)
3.4 Performance Analysis of Cu-Based TSVs
86(6)
3.4.1 Propagation Delay and Power Dissipation
86(1)
3.4.2 Crosstalk-Induced Delay
87(2)
3.4.3 Frequency Response and Bandwidth Analysis
89(3)
3.5 Summary
92(5)
Multiple Choice Questions
93(1)
Short Questions
94(1)
Long Questions
95(1)
References
95(2)
4 Modeling and Performance Analysis of CNT-Based Through Silicon Vias
97(28)
4.1 Introduction
97(2)
4.2 Physical Configuration
99(1)
4.3 Real Possibilities of CNT-Based TSVs
100(1)
4.3.1 Imperfect Metal-Nanotube Contact Resistance
100(1)
4.3.2 Densely Packed CNT Bundles
100(1)
4.3.3 Chirality Control
100(1)
4.3.4 Defect-Free CNTs
100(1)
4.3.5 Higher Growth Temperature of CNTs
101(1)
4.4 Modeling
101(12)
4.4.1 Compact AC Model of SWCNT Bundled TSVs
101(5)
4.4.2 Simplified Transmission Line Model of a TSV Pair
106(4)
4.4.3 Modeling of MWCNT-Based TSV
110(3)
4.5 Performance Analysis
113(5)
4.5.1 Propagation Delay and Power Dissipation Analysis
113(2)
4.5.2 Crosstalk Analysis
115(1)
4.5.3 Frequency Response and Bandwidth Analysis
116(2)
4.6 Conclusion
118(7)
Multiple Choice Questions
120(1)
Short Questions
121(1)
Long Questions
122(1)
References
122(3)
5 Mixed CNT Bundled Through Silicon Vias
125(20)
5.1 Introduction
125(1)
5.2 Configurations of Mixed CNT Bundled TSVs
126(3)
5.2.1 Physical Configuration of a TSV Pair
126(1)
5.2.2 Mixed CNT Bundled TSVs
127(2)
5.3 Modeling of MCB-Based TSVs
129(2)
5.4 Signal Integrity Analysis of MCB-Based TSVs
131(8)
5.4.1 Worst-Case Crosstalk-Induced Delay for Different TSV Pitches
132(2)
5.4.2 In-Phase and Propagation Delay for Different TSV Heights
134(2)
5.4.3 Noise Peak Voltage for Different TSV Heights
136(3)
5.5 Summary
139(6)
Multiple Choice Questions
139(2)
Short Questions
141(1)
Long Questions
141(1)
References
142(3)
6 Graphene Nanoribbon-Based Through Silicon Vias
145(18)
6.1 Introduction
145(1)
6.2 Configurations of GNR-Based TSVs
146(1)
6.3 Fabrication Challenges and Limitations
147(2)
6.4 Modeling of GNR-Based TSVs with Smooth Edges
149(4)
6.5 Modeling of GNR-Based TSVs with Rough Edges
153(1)
6.6 Signal Integrity Analysis of GNR-Based TSVs
154(3)
6.6.1 Propagation Delay for Cu-, SWCNT-, MWCNT-, MCB-, and GNR-Based TSVs
155(1)
6.6.2 Crosstalk-Induced Delay for Cu-, SWCNT-, MWCNT-, MCB-, and GNR-Based TSVs
156(1)
6.7 Summary
157(6)
Multiple Choice Questions
157(2)
Short Questions
159(1)
Long Questions
159(1)
References
160(3)
7 Liners in Through Silicon Vias
163(16)
7.1 Introduction
163(1)
7.2 Types of Liners
164(1)
7.3 Fabrication of TSVs with Polymer Liner
165(2)
7.3.1 Polymer Deep Trench Filling
166(1)
7.4 Modeling of CNT Bundled TSV with SiO2 Liner
167(4)
7.5 Impact of Polymer Liners on Delay
171(3)
7.6 Summary
174(5)
Multiple Choice Questions
174(2)
Short Questions
176(1)
Long Questions
176(1)
References
177(2)
8 Modeling of Through Silicon Vias Using Finite-Difference Time-Domain Technique
179(26)
8.1 Introduction to Finite-Difference Time-Domain Technique
179(2)
8.1.1 Working with the FDTD Method
179(1)
8.1.2 Stability Criterion for FDTD
180(1)
8.1.3 Central Difference Approximation
180(1)
8.2 FDTD Model
181(14)
8.2.1 TSV Line Equation
182(1)
8.2.2 Discretization in Space and Time
182(3)
8.2.3 Leapfrog Time Stepping
185(1)
8.2.4 Incorporation of Boundary Conditions
185(1)
8.2.4.1 Boundary Matching at the Source End
186(1)
8.2.4.2 Boundary Matching at the Load End
187(1)
8.2.5 FDTD Model for TSV Terminated by a Resistive Load
187(1)
8.2.6 FDTD Model for TSV Terminated by a Capacitive Load
188(1)
8.2.7 FDTD Model for TSV Driven by a Resistive Driver
189(2)
8.2.8 FDTD Model for CMOS Gate-Driven TSV
191(3)
8.2.9 FDTD Model for Coupled Transmission Line
194(1)
8.3 Performance Analysis of TSVs
195(5)
8.3.1 Crosstalk Noise
195(1)
8.3.1.1 Functional Crosstalk
196(1)
8.3.1.2 Dynamic Crosstalk
196(2)
8.3.2 Effect of TSV Length Variation
198(2)
8.4 Summary
200(5)
Multiple Choice Questions
201(1)
Short Questions
202(1)
Long Questions
203(1)
References
203(2)
Answers to Multiple Choice Questions 205(2)
Index 207
Brajesh Kumar Kaushik received his Doctorate of Philosophy (PhD) in 2007 from Indian Institute of Technology Roorkee, India. He served Vinytics Peripherals Pvt. Ltd., Delhi, as a Research and Development engineer in microprocessor, microcontroller, and DSP processor-based system design. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor.

He has extensively published in several national and international journals and conferences. He is a reviewer of many international journals belonging to various organizations and publishers including IEEE, IET, Elsevier, Springer, Taylor & Francis, Emerald, ETRI, and PIER. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by government and nongovernment organizations. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and microelectronics. He is Editor-in-Chief of International Journal of VLSI Design & Communication Systems (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; and Journal of Electrical and Electronics Engineering Research (JEEER), Academic Journals.

He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Whos Who in Science and Engineering® and Marquis Whos Who in the World®. His research interests are in the areas of high-speed interconnects, low-power VLSI design, carbon nanotube-based designs, organic electronics. FinFET device circuit co-design, electronic design automation (EDA), and spintronics-based devices and circuits.