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Time Multiplexed Beam-Forming with Space-Frequency Transformation 2013 ed. [Kõva köide]

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  • Formaat: Hardback, 126 pages, kõrgus x laius: 235x155 mm, kaal: 377 g, X, 126 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 23-Aug-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461450454
  • ISBN-13: 9781461450450
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Time Multiplexed Beam-Forming with Space-Frequency Transformation 2013 ed.Suurem pilt
  • Formaat: Hardback, 126 pages, kõrgus x laius: 235x155 mm, kaal: 377 g, X, 126 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 23-Aug-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461450454
  • ISBN-13: 9781461450450
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781461450450.html
Märksõnad:
This book describes a unique approach to smart receiver system design. It starts with the analysis of a very basic, single-path receiver structure, then using similar methods, extends the analysis to a more complicated multi-path receiver.

This book describes a unique approach to smart receiver system design. It starts with the analysis of a very basic, single-path receiver structure, then using similar methods, extends the analysis to a more complicated multi-path receiver. Within the multi-path structure, two different types of phased –array architectures are discussed: Analog beam-forming, and digital beam-forming. The pros and cons are studied, and the gaps are identified. Whereas previous books in this area focus mainly on phased-array circuit implementations, this book fills a gap by providing a system-level approach and introduces new methods for developing smart systems.
1 Introduction
1(6)
1.1 Motivation
1(1)
1.2 Background
2(2)
1.3 Objectives of this Book
4(1)
1.4 Book Outline
5(2)
2 Basic Concepts
7(14)
2.1 Receiver System Basics
7(5)
2.1.1 Noise
7(2)
2.1.2 Non-Linearity
9(2)
2.1.3 Dynamic Range
11(1)
2.2 Phase Modulation Basics
12(3)
2.3 Phased-Array Basics
15(6)
3 Single and Multipath Receiver: A System Approach
21(24)
3.1 Translating ADC Parameters to RF Domain
21(5)
3.1.1 ADC Model
22(1)
3.1.2 ADC Noise
22(2)
3.1.3 ADC Non-Linearity
24(2)
3.2 Mapping ADC Parameters to System Design
26(3)
3.3 Receiver System Optimization Method
29(3)
3.3.1 Receiver Signal Flow Diagram
29(2)
3.3.2 Optimization Method
31(1)
3.4 Analog Beam-Forming
32(5)
3.5 Digital Beam-Forming
37(3)
3.6 General Case of Beam-Forming
40(2)
3.7 Conclusion
42(3)
4 Two-Step Beam-Forming: Multiplexing Architecture
45(6)
4.1 Multiplexing Architecture Introduction
45(3)
4.2 Spatial to Frequency Mapping
48(1)
4.3 Two Steps of Spatial Filtering
48(1)
4.4 Phased-Array Analog and Digital Co-Design
49(1)
4.5 Generalized Phased-Array System Design
49(2)
5 Multiplexing Architecture, Ideal Behavior
51(22)
5.1 Analog Multiplexing
51(6)
5.1.1 Properties of the Switching Signal
52(1)
5.1.2 Pulse Modulation
53(3)
5.1.3 Combination in the Analog Domain
56(1)
5.2 Spatial to Frequency Mapping
57(8)
5.2.1 Space to Frequency Mapping Coefficient Dn
57(4)
5.2.2 Translation from Voltage to Power Domain, Dn to Pxn
61(2)
5.2.3 Coarse Beam Pattern RxN by Frequency Selectivity
63(2)
5.3 Digital De-multiplexing and Phase-Shifting
65(4)
5.4 Array Pattern
69(2)
5.5 Conclusion
71(2)
6 Multiplexing Architecture, Non-Ideal Behavior
73(12)
6.1 Angle Deviation
73(1)
6.2 Non-Ideal Switches
74(3)
6.3 Noise in a Multiplexing System
77(1)
6.4 Frequency Mixing
78(1)
6.5 System Simulations
79(1)
6.6 Power Flow Diagram for a Multiplexed Architecture
80(3)
6.7 Conclusion
83(2)
7 Designs for the 30 GHz Components
85(22)
7.1 Design Requirements
85(1)
7.2 LNA and Multiplexer
86(4)
7.2.1 Circuit Design
86(1)
7.2.2 Measurements
87(3)
7.3 LNA-Multiplexer-Mixer Combination
90(3)
7.3.1 Circuit Design
90(1)
7.3.2 Measurements
91(2)
7.4 Clock Generator
93(4)
7.4.1 Circuit Design
93(1)
7.4.2 Measurements
94(3)
7.5 Input Delay Line
97(3)
7.5.1 Circuit Design
97(2)
7.5.2 Measurements
99(1)
7.6 Power Amplifier
100(6)
7.6.1 Circuit Design
100(2)
7.6.2 Measurements
102(1)
7.6.3 Trouble Shooting
103(3)
7.7 Conclusion
106(1)
8 System Integration and Verification
107(10)
8.1 System with One Channel
107(2)
8.2 System with Four Channels
109(6)
8.2.1 Demonstration with One Input Signal
110(1)
8.2.2 Demonstration with Two Input Signals
111(4)
8.3 Conclusion
115(2)
9 Conclusions
117(4)
Summary 121(2)
References 123