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Top-Down Digital VLSI Design: From Architectures to Gate-Level Circuits and FPGAs [Pehme köide]

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(Head of the Micro-electronics Design Center of ETH, Zurich, Switzerland)
  • Formaat: Paperback / softback, 598 pages, kõrgus x laius: 235x191 mm, kaal: 1180 g
  • Ilmumisaeg: 08-Dec-2014
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0128007303
  • ISBN-13: 9780128007303
Teised raamatud teemal:
Top-Down Digital VLSI Design: From Architectures to Gate-Level Circuits and FPGAsSuurem pilt
  • Formaat: Paperback / softback, 598 pages, kõrgus x laius: 235x191 mm, kaal: 1180 g
  • Ilmumisaeg: 08-Dec-2014
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0128007303
  • ISBN-13: 9780128007303
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780128007303.html
Märksõnad:

Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin’s approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices.

Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more.

  • Demonstrates a top-down approach to digital VLSI design.
  • Provides a systematic overview of architecture optimization techniques.
  • Features a chapter on field-programmable logic devices, their technologies and architectures.
  • Includes checklists, hints, and warnings for various design situations.
  • Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.

Muu info

Top-down approach and system level view of digital design
Preface xv
Acknowledgments xix
Chapter 1 Introduction to Microelectronics 1(40)
1.1 Economic Impact
1(3)
1.2 Microelectronics Viewed From Different Perspectives
4(16)
1.2.1 The Guinness Book of Records Point of View
4(1)
1.2.2 The Marketing Point of View
5(2)
1.2.3 The Fabrication Point of View
7(4)
1.2.4 The Design Engineer's Point of View
11(7)
1.2.5 The Business Point of View
18(2)
1.3 The VLSI Design Flow
20(14)
1.3.1 The Y-chart, a Map of Digital Electronic Systems
20(2)
1.3.2 Major Stages in Digital VLSI Design
22(9)
1.3.3 Cell Libraries
31(1)
1.3.4 Electronic Design Automation Software
32(2)
1.4 Problems
34(1)
1.5 Appendix I: A Brief Glossary of Logic Families
35(2)
1.6 Appendix II: An Illustrated Glossary of Circuit-Related Terms
37(4)
Chapter 2 Field-Programmable Logic 41(22)
2.1 General Idea
41(2)
2.2 Configuration Technologies
43(3)
2.2.1 Static Memory
43(1)
2.2.2 Flash Memory
44(1)
2.2.3 Antifuses
44(2)
2.3 Organization of Hardware Resources
46(7)
2.3.1 Simple Programmable Logic Devices (SPLD)
46(1)
2.3.2 Complex Programmable Logic Devices (CPLD)
47(1)
2.3.3 Field-Programmable Gate Arrays (FPGA)
47(6)
2.4 Commercial Aspects
53(2)
2.4.1 An Overview on FPL Device Families
53(1)
2.4.2 The Price and the Benefits of Electrical Configurability
53(2)
2.5 Extensions of the Basic Idea
55(4)
2.6 The FPL Design Flow
59(2)
2.7 Conclusions
61(2)
Chapter 3 From Algorithms to Architectures 63(116)
3.1 The Goals of Architecture Design
63(2)
3.1.1 Agenda
63(2)
3.2 The Architectural Solution Space
65(22)
3.2.1 The Antipodes
65(6)
3.2.2 What Makes an Algorithm Suitable for a Dedicated VLSI Architecture?
71(3)
3.2.3 There is Plenty of Land Between the Antipodes
74(1)
3.2.4 Assemblies of General-Purpose and Dedicated Processing Units
75(1)
3.2.5 Host Computer with Helper Engines
76(1)
3.2.6 Application-Specific Instruction set Processors
77(2)
3.2.7 Reconfigurable Computing
79(2)
3.2.8 Extendable Instruction set Processors
81(1)
3.2.9 Platform ICs (DSPP)
82(1)
3.2.10 Digest
83(4)
3.3 Dedicated VLSI Architectures and How to Design Them
87(11)
3.3.1 There is Room for Remodeling in the Algorithmic Domain
87(2)
3.3.2 ...and there is Room in the Architectural Domain
89(1)
3.3.3 Systems Engineers and VLSI Designers Must Collaborate
90(2)
3.3.4 A Graph-Based Formalism for Describing Processing Algorithms
92(2)
3.3.5 The Isomorphic Architecture
94(1)
3.3.6 Relative Merits of Architectural Alternatives
95(2)
3.3.7 Computation Cycle Versus Clock Period
97(1)
3.4 Equivalence Transforms for Combinational Computations
98(22)
3.4.1 Common Assumptions
99(1)
3.4.2 Iterative Decomposition
100(3)
3.4.3 Pipelining
103(5)
3.4.4 Replication
108(2)
3.4.5 Time Sharing
110(6)
3.4.6 Associativity Transform
116(1)
3.4.7 Other Algebraic Transforms
117(1)
3.4.8 Digest
118(2)
3.5 Options for Temporary Storage of Data
120(6)
3.5.1 Data Access Patterns
120(1)
3.5.2 Available Memory Configurations and Area Occupation
120(1)
3.5.3 Storage Capacities
121(1)
3.5.4 Wiring and the Costs of Going Off-Chip
122(1)
3.5.5 Latency and Timing
122(1)
3.5.6 Digest
123(3)
3.6 Equivalence Transforms for Non-Recursive Computations
126(7)
3.6.1 Retiming
126(1)
3.6.2 Pipelining Revisited
127(3)
3.6.3 Systolic Conversion
130(1)
3.6.4 Iterative Decomposition and Time Sharing Revisited
130(1)
3.6.5 Replication Revisited
131(1)
3.6.6 Digest
132(1)
3.7 Equivalence Transforms for Recursive Computations
133(15)
3.7.1 The Feedback Bottleneck
133(1)
3.7.2 Unfolding of First-Order Loops
134(3)
3.7.3 Higher-Order Loops
137(2)
3.7.4 Time-Variant Loops
139(1)
3.7.5 Nonlinear or General Loops
140(4)
3.7.6 Pipeline Interleaving, not Quite an Equivalence Transform
144(2)
3.7.7 Digest
146(2)
3.8 Generalizations of the Transform Approach
148(12)
3.8.1 Generalization to other Levels of Detail
148(2)
3.8.2 Bit-Serial Architectures
150(2)
3.8.3 Distributed Arithmetic
152(3)
3.8.4 Generalization to other Algebraic Structures
155(5)
3.8.5 Digest
160(1)
3.9 Conclusions
160(8)
3.9.1 Summary
160(3)
3.9.2 The Grand Architectural Alternatives from an Energy Point of View
163(2)
3.9.3 A Guide to Evaluating Architectural Alternatives
165(3)
3.10 Problems
168(2)
3.11 Appendix I: A Brief Glossary of Algebraic Structures
170(4)
3.12 Appendix II: Area and Delay Figures of VLSI Subfunctions
174(5)
Chapter 4 Circuit Modeling with Hardware Description Languages 179(122)
4.1 Motivation and Background
179(7)
4.1.1 Why Hardware Synthesis?
179(1)
4.1.2 Agenda
179(1)
4.1.3 Alternatives for Modeling Digital Hardware
180(1)
4.1.4 The Genesis of VHDL and SystemVerilog
180(2)
4.1.5 Why Bother Learning Hardware Description Languages?
182(2)
4.1.6 A First Look at VHDL and SystemVerilog
184(2)
4.2 Key Concepts and Constructs of VHDL
186(48)
4.2.1 Circuit Hierarchy and Connectivity
186(4)
4.2.2 Interacting Concurrent Processes
190(8)
4.2.3 A Discrete Replacement for Electrical Signals
198(8)
4.2.4 An Event-Driven Scheme of Execution
206(12)
4.2.5 Facilities for Model Parametrization
218(8)
4.2.6 Concepts Borrowed from Programming Languages
226(8)
4.3 Key Concepts and Constructs of SystemVerilog
234(28)
4.3.1 Circuit Hierarchy and Connectivity
234(3)
4.3.2 Interacting Concurrent Processes
237(6)
4.3.3 A Discrete Replacement for Electrical Signals
243(6)
4.3.4 An Event-Driven Scheme of Execution
249(5)
4.3.5 Facilities for Model Parametrization
254(3)
4.3.6 Concepts Borrowed from Programming Languages
257(5)
4.4 Automatic Circuit Synthesis From HDL Models
262(22)
4.4.1 Synthesis Overview
262(1)
4.4.2 Data Types
263(1)
4.4.3 Finite State Machines and Sequential Subcircuits in General
263(9)
4.4.4 RAM and ROM Macrocells
272(3)
4.4.5 Timing Constraints
275(6)
4.4.6 Limitations and Caveats
281(1)
4.4.7 How to Establish a Register Transfer Level Model Step by Step
282(2)
4.5 Conclusions
284(2)
4.6 Problems
286(3)
4.7 Appendix I: VHDL and SystemVerilog Side by Side
289(4)
4.8 Appendix II: VHDL Extensions and Standards
293(8)
4.8.1 Protected Shared Variables IEEE 1076a
293(1)
4.8.2 The Analog and Mixed-Signal Extension IEEE 1076.1
294(2)
4.8.3 Mathematical Packages for Real and Complex Numbers IEEE 1076.2
296(1)
4.8.4 The Arithmetic Packages IEEE 1076.3
296(1)
4.8.5 The Standard Delay Format (SDF) IEEE 1497
297(1)
4.8.6 A Handy Compilation of Type Conversion Functions
298(2)
4.8.7 Coding Guidelines
300(1)
Chapter 5 Functional Verification 301(56)
5.1 Goals of Design Verification
301(2)
5.1.1 Agenda
302(1)
5.2 How to Establish Valid Functional Specifications
303(4)
5.2.1 Formal Specification
304(1)
5.2.2 Rapid Prototyping
304(2)
5.2.3 Hardware-Assisted Verification
306(1)
5.3 Preparing Effective Simulation and Test Vectors
307(24)
5.3.1 A First Glimpse at VLSI Testing
307(1)
5.3.2 Fully Automated Response Checking is a Must
308(2)
5.3.3 Assertion-Based Verification Checks from Within
310(5)
5.3.4 Exhaustive Verification Remains an Elusive Goal
315(1)
5.3.5 Directed Verification is Indispensable but has its Limitations
316(6)
5.3.6 Directed Random Verification Guards Against Human Omissions
322(5)
5.3.7 Statistical Coverage Analysis Produces Meaningful Metrics
327(1)
5.3.8 Collecting Test Cases from Multiple Sources Helps
328(1)
5.3.9 Separating Test Development from Circuit Design Helps
329(2)
5.4 Consistency and Efficiency Considerations
331(10)
5.4.1 A Coherent Schedule for Simulation and Test
332(3)
5.4.2 Protocol Adapters Help Reconcile Different Views on Data and Latency
335(3)
5.4.3 Calculating High-Level Figures of Merit
338(1)
5.4.4 Patterning Simulation Set-Ups after the Target System
339(1)
5.4.5 Initialization
340(1)
5.4.6 Trimming Run Times by Skipping Redundant Simulation Sequences
340(1)
5.5 Testbench Coding and HDL Simulation
341(5)
5.5.1 Modularity and Reuse are the Keys to Testbench Design
341(1)
5.5.2 Anatomy of a File-Based Testbench
342(4)
5.6 Conclusions
346(1)
5.7 Problems
347(3)
5.8 Appendix I: Formal Approaches to Functional Verification
350(2)
5.9 Appendix II: Deriving a Coherent Schedule for Simulation and Test
352(5)
Chapter 6 The Case for Synchronous Design 357(34)
6.1 Introduction
357(2)
6.2 The Grand Alternatives for Regulating State Changes
359(5)
6.2.1 Synchronous Clocking
360(1)
6.2.2 Asynchronous Clocking
360(1)
6.2.3 Self-Timed Clocking
361(3)
6.3 Why a Rigorous Approach to Clocking is Essential in VLSI
364(6)
6.3.1 The Perils of Hazards
364(1)
6.3.2 The Pros and Cons of Synchronous Clocking
365(2)
6.3.3 Clock-as-Clock-Can is not an Option in VLSI
367(1)
6.3.4 Fully Self-Timed Clocking is not Normally an Option Either
368(1)
6.3.5 Hybrid Approaches to System Clocking
368(2)
6.4 The Dos and Donts of Synchronous Circuit Design
370(10)
6.4.1 First Guiding Principle: Dissociate Signal Classes!
370(1)
6.4.2 Second Guiding Principle: Allow for Circuits to Settle Before Clocking!
371(1)
6.4.3 Synchronous Design Rules at a More Detailed Level
372(8)
6.5 Conclusions
380(1)
6.6 Problems
381(1)
6.7 Appendix: On Identifying Signals
382(9)
6.7.1 Signal Class
382(2)
6.7.2 Active Level
384(1)
6.7.3 Signaling Waveforms
385(1)
6.7.4 Three-State Capability
386(1)
6.7.5 Inputs, Outputs and Bidirectional Ports
386(1)
6.7.6 Present State vs. Next State
387(1)
6.7.7 Signal Naming Convention Syntax
387(1)
6.7.8 Usage of Upper and Lower Case Letters in HDL Source Code
388(1)
6.7.9 A Note on the Portability of Names Across EDA Platforms
389(2)
Chapter 7 Clocking of Synchronous Circuits 391(54)
7.1 What is the Difficulty With Clock Distribution?
391(3)
7.1.1 Agenda
392(1)
7.1.2 Timing Quantities Related to Clock Distribution
393(1)
7.2 How Much Skew and Jitter Does a Circuit Tolerate?
394(22)
7.2.1 Basics
394(2)
7.2.2 Single-Edge-Triggered One-Phase Clocking
396(6)
7.2.3 Dual-Edge-Triggered One-Phase Clocking
402(2)
7.2.4 Symmetric Level-Sensitive Two-Phase Clocking
404(3)
7.2.5 Unsymmetric Level-Sensitive Two-Phase Clocking
407(4)
7.2.6 Single-Wire Level-Sensitive Two-Phase Clocking
411(1)
7.2.7 Level-Sensitive One-Phase Clocking and Wave Pipelining
412(4)
7.3 How to Keep Clock Skew Within Tight Bounds
416(7)
7.3.1 Clock Waveforms
416(1)
7.3.2 Collective Clock Buffers
417(2)
7.3.3 Distributed Clock Buffer Trees
419(2)
7.3.4 Hybrid Clock Distribution Networks
421(1)
7.3.5 Clock Skew Analysis
421(2)
7.4 How to Achieve Friendly Input/Output Timing
423(9)
7.4.1 Friendly as Opposed to Unfriendly I/0 Timing
423(1)
7.4.2 Impact of Clock Distribution Delay on I/0 Timing
424(2)
7.4.3 Impact of PTV Variations on I/0 Timing
426(1)
7.4.4 Registered Inputs and Outputs
427(1)
7.4.5 Adding Artificial Contamination Delay to Data Inputs
427(1)
7.4.6 Driving Input Registers From an Early Clock
428(1)
7.4.7 Clock Tapped From Slowest Component in Clock Domain
428(1)
7.4.8 "Zero-Delay" Clock Distribution by Way of a DLL or PLL
429(3)
7.5 How to Implement Clock Gating Properly
432(6)
7.5.1 Traditional Feedback-Type Registers with Enable
432(1)
7.5.2 A Crude and Unsafe Approach to Clock Gating
433(1)
7.5.3 A Simple Clock Gating Scheme that May Work Under Certain Conditions
434(1)
7.5.4 Safe Clock Gating Schemes
434(4)
7.6 Summary
438(3)
7.7 Problems
441(4)
Chapter 8 Acquisition of Asynchronous Data 445(28)
8.1 Motivation
445(2)
8.2 Data Consistency in Vectored Acquisition
447(10)
8.2.1 Plain Bit-Parallel Synchronization
447(1)
8.2.2 Unit-Distance Coding
448(1)
8.2.3 Suppression of Jumbled Data Patterns
449(1)
8.2.4 Handshaking
450(3)
8.2.5 Partial Handshaking
453(1)
8.2.6 FIFO Synchronizers
454(3)
8.3 Data Consistency in Scalar Acquisition
457(3)
8.3.1 No Synchronization Whatsoever
457(1)
8.3.2 Synchronization at Multiple Places
457(1)
8.3.3 Synchronization at a Single Place
458(1)
8.3.4 Synchronization From a Slow Clock
458(2)
8.4 Marginal Triggering and Metastability
460(10)
8.4.1 Metastability and How it Becomes Manifest
460(3)
8.4.2 Repercussions on Circuit Functioning
463(1)
8.4.3 A Statistical Model for Estimating Synchronizer Reliability
464(2)
8.4.4 Plesiochronous Interfaces
466(1)
8.4.5 Containment of Metastable Behavior
466(4)
8.5 Summary
470(1)
8.6 Problems
471(2)
Appendix A Elementary Digital Electronics 473(50)
A.1 Introduction
473(5)
A.1.1 Common Number Representation Schemes
473(2)
A.1.2 Floating Point Number Formats
475(2)
A.1.3 Notational Conventions for Two-Valued Logic
477(1)
A.2 Theoretical Background of Combinational Logic
478(13)
A.2.1 Truth Table
478(1)
A.2.2 The n-Cube
479(1)
A.2.3 Karnaugh Map
479(1)
A.2.4 Program Code
479(1)
A.2.5 Logic Equations
480(2)
A.2.6 Two-Level Logic
482(1)
A.2.7 Multi-Level Logic
483(1)
A.2.8 Symmetric and Monotone Functions
484(1)
A.2.9 Threshold Functions
485(1)
A.2.10 Complete Gate Sets
485(1)
A.2.11 Multi-Output Functions
486(1)
A.2.12 Logic Minimization
487(4)
A.3 Circuit Alternatives for Implementing Combinational Logic
491(5)
A.3.1 Random Logic
491(1)
A.3.2 Programmable Logic Array (PLA)
491(2)
A.3.3 Read-Only Memory (ROM)
493(1)
A.3.4 Array Multiplier
493(1)
A.3.5 Digest
494(2)
A.4 Bistables and Other Memory Circuits
496(12)
A.4.1 Flip-Flops or Edge-Triggered Bistables
497(3)
A.4.2 Latches or Level-Sensitive Bistables
500(1)
A.4.3 Unclocked Bistables
501(5)
A.4.4 Random Access Memories (RAM)
506(2)
A.5 Transient Behavior of Logic Circuits
508(5)
A.5.1 Glitches, a Phenomenological Perspective
508(1)
A.5.2 Function Hazards, a Circuit-Independent Mechanism
509(1)
A.5.3 Logic Hazards, a Circuit-Dependent Mechanism
510(2)
A.5.4 Digest
512(1)
A.6 Timing Quantities
513(6)
A.6.1 Delay Parameters Serve for Combinational and Sequential Circuits
513(2)
A.6.2 Timing Conditions Get Imposed by Sequential Circuits Only
515(2)
A.6.3 Secondary Timing Quantities are Derived From Primary Ones
517(1)
A.6.4 Timing Constraints Address Synthesis Needs
518(1)
A.7 Basic Microprocessor Input/Output Transfer Protocols
519(2)
A.8 Summary
521(2)
Appendix B Finite State Machines 523(20)
B.1 Abstract Automata
523(11)
B.1.1 Mealy Machine
524(1)
B.1.2 Moore Machine
525(1)
B.1.3 Medvedev Machine
526(1)
B.1.4 Relationships Between Finite State Machine Models
527(4)
B.1.5 Taxonomy of Finite State Machines
531(1)
B.1.6 State Reduction
532(2)
B.2 Practical Aspects and Implementation Issues
534(8)
B.2.1 Parasitic States and Symbols
534(2)
B.2.2 Mealy-, Moore-, Medvedev-Type, and Combinational Output Bits
536(1)
B.2.3 Through Paths and Logic Instability
537(1)
B.2.4 Switching Hazards
538(1)
B.2.5 Hardware Costs
539(3)
B.3 Summary
542(1)
Appendix C Symbols and Constants 543(10)
C.1 Abbreviations
543(1)
C.2 Mathematical Symbols
544(4)
C.3 Physical and Material Constants
548(5)
Bibliography 553(12)
Index 565
Since 1989, Hubert Kaeslin has headed the Micro-electronics Design Center of ETH Zurich, which taped out more than 300 circuit designs under his supervision over the past 23 years, both for research and educational purposes. He has written more than 75 scientific papers and his professional interests extend to digital signal processing, IT security, graph theory, and visual formalisms. Dr. Kaeslin is a Senior Member of IEEE and has been awarded the title of professor by ETH in 2010.