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Verilog HDL Design Examples [Kõva köide]

(Santa Clara University, California, USA)
  • Formaat: Hardback, 674 pages, kõrgus x laius: 254x178 mm, kaal: 1390 g, 34 Tables, black and white; 698 Line drawings, black and white
  • Ilmumisaeg: 13-Oct-2017
  • Kirjastus: CRC Press
  • ISBN-10: 1138099953
  • ISBN-13: 9781138099951
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Verilog HDL Design ExamplesSuurem pilt
  • Formaat: Hardback, 674 pages, kõrgus x laius: 254x178 mm, kaal: 1390 g, 34 Tables, black and white; 698 Line drawings, black and white
  • Ilmumisaeg: 13-Oct-2017
  • Kirjastus: CRC Press
  • ISBN-10: 1138099953
  • ISBN-13: 9781138099951
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Teised raamatud sellest sooduspakkumisest: Taylor & Francis teadusraamatud International Student Editions hindadega
Püsilink: https://www.kriso.ee/db/9781138099951.html
Märksõnad:

The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).

Arvustused

"This book is an invaluable introduction to the theory of hardware design for any Computer Systems Engineering program." Kyle D. Gilsdorf, Arizona State University, USA





"Professor Cavanagh is a unique technical writer capable of educating the novice to professional technician. His work provides complete examples and clear succinct descriptions. His textbooks are a timepiece reference that can be easily referenced when the need arises. Geri Lamble, Foothill College, California, USA

"As a design engineer working in industry with 20+ years experience, Verilog HSD has become the predominant language of choice for designing chip. There are many text books that teach Verilog HDL. Some provide good logic design examples. This text book, however, is rich in examples. As such, this would be the book Id first reference if the need arises." Steven Midford, Engineer "This book is an invaluable introduction to the theory of hardware design for any Computer Systems Engineering program." Kyle D. Gilsdorf, Arizona State University, USA





"Professor Cavanagh is a unique technical writer capable of educating the novice to professional technician. His work provides complete examples and clear succinct descriptions. His textbooks are a timepiece reference that can be easily referenced when the need arises. Geri Lamble, Foothill College, California, USA





"As a design engineer working in industry with 20+ years experience, Verilog HSD has become the predominant language of choice for designing chip. There are many text books that teach Verilog HDL. Some provide good logic design examples. This text book, however, is rich in examples. As such, this would be the book Id first reference if the need arises." Steven Midford, Engineer

Preface xi
Chapter 1 Introduction to Logic Design Using Verilog HDL
1(144)
1.1 Logic Elements
2(15)
1.1.1 Comments
2(1)
1.1.2 Logic Gates
2(3)
1.1.3 Logic Macro Functions
5(9)
1.1.4 Procedural Flow Control
14(2)
1.1.5 Net Data Types
16(1)
1.1.6 Register Data Types
16(1)
1.2 Expressions
17(11)
1.2.1 Operands
18(1)
1.2.2 Operators
19(9)
1.3 Modules and Ports
28(3)
1.3.1 Designing a Test Bench for Simulation
29(2)
1.4 Built-In Primitives
31(20)
1.4.1 Built-In Primitives Design Examples
35(16)
1.5 User-Defined Primitives
51(18)
1.5.1 Defining a User-Defined Primitive
52(1)
1.5.2 Combinational User-Defined Primitives
52(11)
1.5.3 Sequential User-Defined Primitives
63(6)
1.6 Dataflow Modeling
69(18)
1.6.1 Continuous Assignment
69(2)
1.6.2 Reduction Operators
71(3)
1.6.3 Conditional Operators
74(3)
1.6.4 Relational Operators
77(2)
1.6.5 Logical Operators
79(2)
1.6.6 Bitwise Operators
81(3)
1.6.7 Shift Operators
84(3)
1.7 Behavioral Modeling
87(21)
1.7.1 Initial Statement
87(1)
1.7.2 Always Statement
88(2)
1.7.3 Intrastatement Delay
90(1)
1.7.4 Interstatement Delay
91(1)
1.7.5 Blocking Assignments
91(1)
1.7.6 Nonblocking Assignments
91(1)
1.7.7 Conditional Statements
92(3)
1.7.8 Case Statement
95(3)
1.7.9 Loop Statements
98(6)
1.7.10 Logical, Algebraic, and Rotate Shift Operations
104(4)
1.8 Structural Modeling
108(21)
1.8.1 Module Instantiation
109(1)
1.8.2 Ports
109(2)
1.8.3 Design Examples
111(18)
1.9 Tasks and Functions
129(11)
1.9.1 Task Declaration
129(1)
1.9.2 Task Invocation
130(4)
1.9.3 Function Declaration
134(1)
1.9.4 Function Invocation
135(5)
1.10 Problems
140(5)
Chapter 2 Combinational Logic Design Using Verilog HDL
145(100)
2.1 Number Systems
146(2)
2.1.1 Binary Number System
146(1)
2.1.2 Octal Number System
147(1)
2.1.3 Decimal Number System
147(1)
2.1.4 Hexadecimal Number System
148(1)
2.2 Boolean Algebra
148(6)
2.2.1 Axioms
149(1)
2.2.2 Theorems
150(2)
2.2.3 Other Terms for Boolean Algebra
152(2)
2.3 Logic Equations
154(11)
2.4 Multiplexers
165(11)
2.5 Comparators
176(9)
2.6 Programmable Logic Devices
185(29)
2.6.1 Programmable Read-Only Memories
185(6)
2.6.2 Programmable Array Logic
191(11)
2.6.3 Programmable Logic Array
202(12)
2.7 Additional Design Examples
214(24)
2.8 Problems
238(7)
Chapter 3 Sequential Logic Design Using Verilog HDL
245(162)
3.1 Introduction
245(2)
3.1.1 Definition of a Sequential Machine
245(2)
3.2 Synchronous Sequential Machines
247(74)
3.2.1 Synthesis Procedure
247(1)
3.2.2 Equivalent States
248(1)
3.2.3 Moore Machines
248(25)
3.2.4 Mealy Machines
273(26)
3.2.5 Synchronous Registers
299(12)
3.2.6 Synchronous Counters
311(10)
3.3 Asynchronous Sequential Machines
321(33)
3.3.1 Synthesis Procedure
323(1)
3.3.2 Hazards
324(2)
3.3.3 Oscillations
326(2)
3.3.4 Races
328(2)
3.3.5 Design Examples of Asynchronous Sequential Machines
330(24)
3.4 Pulse-Mode Asynchronous Sequential Machines
354(41)
3.4.1 Synthesis Procedure
356(1)
3.4.2 SR Latches with D Flip-Flops as Storage Elements
356(16)
3.4.3 T Flip-Flops as Storage Elements
372(23)
3.5 Problems
395(12)
Chapter 4 Computer Arithmetic Design Using Verilog HDL
407(144)
4.1 Introduction
407(1)
4.2 Fixed-Point Addition
407(16)
4.2.1 Full Adder
408(3)
4.2.2 Three-Bit Adder
411(4)
4.2.3 Four-Bit Ripple-Carry Adder
415(3)
4.2.4 Carry Lookahead Adder
418(5)
4.3 Fixed-Point Subtraction
423(16)
4.3.1 Four-Bit Ripple Subtractor
425(3)
4.3.2 Eight-Bit Subtractor
428(2)
4.3.3 Four-Bit Dataflow Adder/Subtractor
430(5)
4.3.4 Eight-Bit Behavioral Adder/Subtractor
435(4)
4.4 Fixed-Point Multiplication
439(11)
4.4.1 Behavioral Four-Bit Multiplier
441(3)
4.4.2 Three-Bit Array Multiplier
444(4)
4.4.3 Four-Bit Dataflow Multiplication Using the Multiply Operator
448(2)
4.5 Fixed-Point Division
450(5)
4.6 Arithmetic and Logic Unit
455(4)
4.7 Decimal Addition
459(13)
4.7.1 Decimal Addition with Sum Correction
462(4)
4.7.2 Decimal Addition Using Multiplexers for Sum Correction
466(6)
4.8 Decimal Subtraction
472(19)
4.8.1 Decimal Subtraction Using Full Adders and Built-In Primitives for Four Bits
475(3)
4.8.2 Decimal/Binary Subtraction Using Full Adders and Built-In Primitives for Eight Bits
478(4)
4.8.3 Eight-Bit Decimal Subtraction Unit with Built-in Primitives and Full Adders Designed Using Behavioral Modeling
482(9)
4.9 Decimal Multiplication
491(4)
4.10 Decimal Division
495(8)
4.11 Floating-Point Addition
503(9)
4.12 Floating-Point Subtraction
512(15)
4.12.1 True Addition and True Subtraction
516(11)
4.13 Floating-Point Multiplication
527(8)
4.14 Floating-Point Division
535(7)
4.15 Problems
542(9)
Appendix A Event Queue 551(16)
Appendix B Verilog Project Procedure 567(2)
Appendix C Answers to Select Problems 569(74)
Index 643
Joseph Cavanagh received his Bachelor of Science in Electrical Engineering from Indiana Institute of Technology and his Master of Science from Santa Clara University. He spent twenty-two years teaching in the Department of Computer Engineering at Santa Clara University. Prior to that, he taught in the Computer Engineering Department at San Jose State University. Currently, he is an Associate Professor in the Department of Electrical Engineering at Cogswell Polytechnical College, where he has been for the past twelve years. Additionally, he has over two decades of experience designing computing equipmentincluding arithmetic processors, instruction fetch units, and peripheral control unitsfor such companies as International Business Corporation, Amdahl Corporation, and Digital Equipment Corporation. Joseph Cavanagh is a member of IEEE, IEEE Computer Society, Tau Beta Pi, and the author of six publications.