Muutke küpsiste eelistusi

VHDL 101: Everything you Need to Know to Get Started [Pehme köide]

3.50/5 (3 hinnangut Goodreads-ist)
(Curriculum Developer, Xilinx Inc., St. Louis, MO, USA)
  • Formaat: Paperback / softback, 200 pages, kõrgus x laius: 235x191 mm, kaal: 390 g
  • Ilmumisaeg: 28-Jan-2011
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • ISBN-10: 1856177041
  • ISBN-13: 9781856177047
Teised raamatud teemal:
VHDL 101: Everything you Need to Know to Get StartedSuurem pilt
  • Formaat: Paperback / softback, 200 pages, kõrgus x laius: 235x191 mm, kaal: 390 g
  • Ilmumisaeg: 28-Jan-2011
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • ISBN-10: 1856177041
  • ISBN-13: 9781856177047
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781856177047.html
Märksõnad:
VHDL 101 is written for Electrical Engineers and others wishing to break into FPGA design and assumes a basic knowledge of digital design and some experience with engineering process.

Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VHDL (VHSIC Hardware Description Language) as well as commands and data types. Extensive simple, complete designs accompany the content for maximum comprehension. The book concludes with a section on design re-use, which is of utmost importance to today's engineer who needs to meet a deadline and lower costs per unit.

-Gets you up to speed with VHDL fast, reducing time to market and driving down costs

-Companion website with source code and other documents to assist the student in building the reference design used throughout the book

-Covers the basics including language concepts and includes complete design examples for ease of learning

-Covers widely accepted industry nomenclature

-Learn from best design practices



Muu info

Learn how to utilize VDHL for FPGA development
Preface ix
About the Author xiii
Acknowledgments xv
Chapter 1 Introduction and Background 1(10)
1.1 VHDL
1(1)
1.2 Brief History of VHDL
2(2)
1.2.1 Coding Styles: Structural vs. Behavioral vs. RTL
3(1)
1.3 FPGA Architecture
4(7)
1.3.1 Creating the Design
7(4)
Chapter 2 Overview of the Process of Implementing an FPGA Design 11(8)
2.1 Design Entry
11(2)
2.2 Synthesis
13(1)
2.3 Simulation
14(3)
2.4 Implementation
17(1)
2.4.1 Translate
17(1)
2.4.2 Map
17(1)
2.4.3 Place and Route
17(1)
2.5 Bitstream Generation
18(1)
Chapter 3 Loop 1 — Going with the Flow 19(72)
3.1 The Shape of VHDL
19(72)
3.1.1 The Many Levels of Comments
21(4)
3.1.2 Library and Package Inclusion
25(2)
3.1.3 Entity
27(1)
3.1.4 Architecture
28(1)
3.1.5 Configuration Statements
29(1)
3.1.6 Signals, Data Types, Logical Operators
30(29)
3.1.7 Concurrent Statements
59(18)
3.1.8 Baud Rate Generator
77(1)
3.1.9 Transmitter
77(1)
3.1.10 Receiver
78(5)
3.1.11 Introducing the Simulation Environment
83(8)
Chapter 4 Loop 2 — Going Deeper 91(52)
4.1 Introducing Processes, Variables, and Sequential Statements
91(48)
4.1.1 Variables
101(4)
4.1.2 Signals within processes
105(8)
4.1.3 Sequential Statements
113(26)
4.2 Tool Perspectives — Synthesis Options and Constraints
139(4)
4.2.1 Synthesis Options
139(2)
4.2.2 Constraints
141(2)
Chapter 5 Loop 3 143(50)
5.1 Introducing Concept of Reuse
143(7)
5.1.1 A Little More on Libraries and Packages
145(5)
5.2 Flexibility Using Generics and Constants
150(3)
5.3 Generate Statements
153(12)
5.3.1 Conditional Generate Form
153(3)
5.3.2 Generate Loop Form
156(9)
5.4 Functions and Procedures
165(11)
5.4.1 Function and Procedure Parameters
168(1)
5.4.2 Overloading
169(1)
5.4.3 When to Use Procedures and Functions
170(2)
5.4.4 Using Functions and Procedures
172(4)
5.5 Attributes
176(4)
5.6 Packages
180(5)
5.6.1 Organizing and Creating a Library
185(1)
5.7 Commonly Used Libraries
185(8)
5.7.1 Simulation Packages
185(1)
5.7.2 IEEE_1164
186(1)
5.7.3 NUMERIC_STD
187(2)
5.7.4 TEXTIO
189(4)
Appendix: A Quick Reference 193(4)
A.1 Language Constructs
193(1)
A.2 Data Types
194(1)
A.3 Standard Libraries
194(3)
Index 197