The purpose of VHDL Modeling for Digital Design Synthesis is to introduce VHSIC Hardware Description Language (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages.
VHDL was originally introduced as a hardware description language that permitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the implementation technology. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. This book covers the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum.
VHDL Modeling for Digital Design Synthesis is designed for working professionals as well as for graduate or undergraduate students. Readers can use this book to get acquainted with VHDL and to learn how it can be used in modeling of digital designs.
Intended for working professionals as well as students, this book introduces VHSIC Hardware Description Language (VHDL) and its use for synthesis. VHDL, a hardware description language which provides a means of specifying a digital system over different levels of abstraction, supports behavior specifications during the early stages of design process and structural specifications during later implementation stages. The first six chapters introduce the features of VHDL. Topics include a brief history of VHDL and how it is used in the design world; basic structures in VHDL; types, operators, and expressions; sequential statements; concurrent statements; and subprograms and packages. The second section (Chapters 7 to 14) discusses modeling at various levels of abstraction, the concept of synthesis, and how to write efficient VHDL design descriptions. Annotation copyright Book News, Inc. Portland, Or.
VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as a hardware description language that permitted the simulation of digital designs, VHDL is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this is that not all of its constructs are useful in synthesis. VHDL has data structures, such as files and pointers, which are useful for simulation but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. VHDL Modeling for Digital Design Synthesis covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum.
Audience: Working professionals as well as graduate or undergraduate students who can use the book to get acquainted with VHDL and to learn how it can be used in modeling or digital design.
