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VLIW Microprocessor Hardware Design [Kõva köide]

  • Formaat: Hardback, 219 pages, kõrgus x laius x paksus: 231x155x20 mm, kaal: 492 g
  • Ilmumisaeg: 16-Oct-2007
  • Kirjastus: McGraw-Hill Professional
  • ISBN-10: 0071497021
  • ISBN-13: 9780071497022
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VLIW Microprocessor Hardware DesignSuurem pilt
  • Formaat: Hardback, 219 pages, kõrgus x laius x paksus: 231x155x20 mm, kaal: 492 g
  • Ilmumisaeg: 16-Oct-2007
  • Kirjastus: McGraw-Hill Professional
  • ISBN-10: 0071497021
  • ISBN-13: 9780071497022
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780071497022.html
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Acquire the Design Information, Methods, and SkillsNeeded to Master the New VLIW Architecture!

VLIW Microprocessor Hardware Design offers you a complete guide to VLIW hardware designproviding state-of-the-art coverage of microarchitectures, RTL coding, ASIC flow, and FPGA flow of design. The book also contains a wide range of skills-building examples, all worked using Verilog, that equip you with a practical, hands-on tutorial for understanding each step in the VLIW microprocessor design process.

Written by Weng Fook Lee, an internationally renowned expert in the field of microprocessor design, this cutting-edge hardware design tool presents unsurpassed coverage of the latests in VLIW microprocessing. Authoritative and comprehensive, VLIW Microprocessor Hardware Design features:





Step-by-step information on the VLIW hardware design process A wealth of Verilog-based designs ASIC and FPGA implementations Expert guidance on the best-known methods for RTL coding Over 75 detailed illustrations that clarify each aspect of VLIW design

Inside this Complete VLIW Microprocessor Toolkit

Introduction Design Methodology RTL Coding, Testbenching, and Simulation FPGA Implementation Testbenches and Simulation Results Synthesis Results and Gate Level Netlist
Preface ix
Acknowledgments xiii
Trademarks xv
Chapter
1. Introduction		 1
1.1 Types of Microprocessors
3
1.2 Types of Microprocessor Architecture
3
Chapter
2. Design Methodology		 9
2.1 Technical Specification
9
2.1.1 Instruction Set of VLIW Microprocessor
11
2.1.2 Definition of Opcode for VLIW Instruction Set
13
2.1.3 Definition of VLIW Instruction
18
2.2 Architectural Specification
19
2.3 Microarchitecture Specification
23
Chapter
3. RTL Coding, Testbenching, and Simulation		 33
3.1 Coding Rules
34
3.2 RTL Coding
46
3.2.1 Module fetch RTL Code
46
3.2.2 Module decode RTL Code
59
3.2.3 Module register file RTL Code
69
3.2.4 Module execute RTL Code
83
3.2.5 Module writeback RTL Code
138
3.2.6 Module vliwtop RTL Code
143
3.3 Testbenches and Simulation
147
3.3.1 Creating and Using a Testplan
148
3.3.2 Code Coverage
148
3.4 Synthesis
151
3.4.1 Standard Cell Library
152
3.4.2 Design Constraints
156
3.4.3 Synthesis Tweaks
157
3.5 Formal Verification
159
3.6 Pre-layout Static Timing Analysis
159
3.7 Layout
162
3.7.1 Manual/Custom Layout
163
3.7.2 Semi-custom/Auto Layout
164
3.7.3 Auto Place and Route
164
3.8 DRC / LVS
165
3.9 RC Extraction
166
3.10 Post-layout Logic Verification
166
3.11 Post-layout Performance Verification
167
3.12 Tapeout
167
3.13 Linking Front End and Back End
168
3.14 Power Consumption
171
3.15 ASIC Design Testability
172
Chapter
4. FPGA Implementation		 175
4.1 FPGA Versus ASIC
175
4.2 FPGA Design Methodology
176
4.3 Testing FPGA
177
4.4 Structured ASIC
178
Appendix A. Testbenches and Simulation Results 181
Appendix B. Synthesis Results, Gate Level Netlist 201
Bibliography 207
Index 209


Weng Fook Lee (Penang, Malaysia) is a distinguished Senior Member of Technical Staff at Emerald Systems Design Center. He is an acknowledged expert in the field of RTL coding and logic synthesis, with vast experience in microprocessor design, chipsets, ASIC and SOC devices. He holds 14 design patents and is the author of a VHDL book with Academic Press.