The first encompassing treatise of this new, but very important field puts the known physical limitations for classic 2D electronics into perspective with the requirements for further electronics developments and market necessities. This two-volume handbook presents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packaging technology, and thermal aspects.
It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integration to the semiconductor roadmap of the industry, before going on to cover processing technology and 3D structure fabrication strategies in detail. This is followed by fields of application and a look at the future of 3D integration.
The contributions come from key players in the field, from both academia and industry, including such companies as Lincoln Labs, Fraunhofer, RPI, ASET, IMEC, CEA-LETI, IBM, and Renesas.
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1 Introduction to 3D Integration |
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2 Drivers for 3D Integration |
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3 Overview of 3D Process Technology |
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Through Silicon Via Fabrication |
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4 Deep Reactive Ion Etching |
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9 Metallization by chemical vapor deposition of W and Cu |
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Wafer Thinning and Bonding Technology |
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10 Fabrication, Processing and Singulation of Thin Wafers |
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11 Overview of Bonding Technologies for 3D Integration |
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12 Chip-to-Wafer and Wafer-to-Wafer Integration Schemes |
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13 Polymer Adhesive Bonding Technology |
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14 Bonding with Intermetallic Compounds |
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17 Interconnect Process at the University of Arkansas |
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18 Vertical Interconnection by ASET at Toshiba |
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19 3D Integration at CEA-LETI |
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20 Lincoln Laboratory's Integration Technology |
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21 3D Integration Technologies at IMEC |
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22 Fabrication Using Copper Thermo-Compression Bonding at MIT |
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23 Rensselaer 3D Integration Processes |
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24 3D Integration at Tezzaron Semiconductor Corporation |
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25 3D Integration at Ziptronix, Inc. |
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26 3D Integration at ZyCube Sendai Lab. |
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Design, Performance, and Thermal Management |
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27 Design for 3D Integration at NC State University |
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28 Design for 3D Integration at Fraunhofer IIS-EAS |
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29 Multiproject Circuit Design and Layout in Lincoln Laboratory's 3D Technology |
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30 Computer-aided Design for 3D Circuits at the University of Minnesota |
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31 Electrical Performance of 3D Circuits |
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32 Testing of 3D Circuits |
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33 Thermal Management of Vertically Integrated Packages at IBM Zurich |
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34 3D and Microprocessors |
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38 Wireless Sensor Systems - |
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Dr. Philip Garrou, from Microelectronic Consultants of North Carolina, specializes in thin film microelectronic materials and applications, prior to which he was Director of Technology and New Business Development for Dow Chemicals' Advanced Electronic Materials business. He is a fellow of IEEE and IMAPS, has served as Associate Editor of the IEEE Transactions on Advanced Packaging, has authored two microelectronics texts and is co-author of over 75 peer reviewed publications and book chapters. Dr. Christopher A. Bower is Senior Research Scientists at Semprius Inc., Durham, NC, where he works on heterogeneous integration of compound semiconductor devices. He previously held positions at Inplane Photonics as a senior process development engineer and as a scientist at RTI International, where he participated in multiple DARPA-funded 3D integration programs. Dr. Bower has authored or co-authored over 40 peer-reviewed publications and holds 2 U.S. patents. Dr. Peter Ramm is head of the silicon technology department of Fraunhofer IZM in Munich, Germany, where he is responsible for process integration of innovative devices and new materials. Peter Ramm received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility. In 1988 he joined Fraunhofer IFT in Munich, focusing since two decades on 3D integration technologies. Dr. Ramm is author or co-author of more than 50 papers and 20 patents.
