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Handbook of 3D Integration, Volumes 1 and 2: Technology and Applications of 3D Integrated Circuits [Pehme köide]

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Edited by (Fraunhofer Institute IZM, Munich, Germany), Edited by (Semprius Inc., Raleigh, USA), Edited by (Research Triangle Park, USA)
  • Formaat: Paperback / softback, 799 pages, kõrgus x laius x paksus: 241x170x43 mm, kaal: 1656 g
  • Ilmumisaeg: 19-Sep-2012
  • Kirjastus: Blackwell Verlag GmbH
  • ISBN-10: 3527332650
  • ISBN-13: 9783527332656
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Handbook of 3D Integration, Volumes 1 and 2: Technology and Applications of 3D Integrated CircuitsSuurem pilt
  • Formaat: Paperback / softback, 799 pages, kõrgus x laius x paksus: 241x170x43 mm, kaal: 1656 g
  • Ilmumisaeg: 19-Sep-2012
  • Kirjastus: Blackwell Verlag GmbH
  • ISBN-10: 3527332650
  • ISBN-13: 9783527332656
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783527332656.html
The first encompassing treatise of this new and very important field puts the known physical limitations for classic 2D microelectronics into perspective with the requirements for further microelectronics developments and market necessities. This two-volume handbook presents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packaging technology, and thermal aspects. It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integration to the semiconductor roadmap of the industry. Before going on to cover processing technology and 3D structure fabrication strategies in detail. This is followed by fields of application and a look at the future of 3D integration.

The editors have assembled contributions from key academic and industrial players in the field, including Intel, Micron, IBM, Infineon, Qimonda, NXP, Philips, Toshiba, Semitool, EVG, Tezzaron, Lincoln Labs, Fraunhofer, RPI, IMEC, CEA-LETI and many others.
Preface xvii
List of Contributors
xix
1 Introduction to 3D Integration
1(12)
Philip Garrou
1.1 Introduction
1(2)
1.2 Historical Evolution of Stacked Wafer Concepts
3(1)
1.3 3D Packaging vs 3D Integration
4(2)
1.4 Non-TSV 3D Stacking Technologies
6(7)
1.4.1 Irvine Sensors
6(1)
1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona
6(1)
1.4.3 Fujitsu
7(2)
1.4.4 Fraunhofer/IZM
9(1)
1.4.5 3D Plus/Leti
10(1)
1.4.6 Toshiba System Block Module
11(1)
References
11(2)
2 Drivers for 3D Integration
13(12)
Philip Garrou
Susan Vitkavage
Sitaram Arkalgud
2.1 Introduction
13(1)
2.2 Electrical Performance
13(6)
2.2.1 Signal Seed
14(3)
2.2.2 Memory Latency
17(2)
2.3 Power Consumption and Noise
19(1)
2.3.1 Noise
19(1)
2.4 Form Factor
19(3)
2.4.1 Non-Volatile Memory Technology: Flash
20(1)
2.4.2 Volatile Memory Technology: SRAM and DRAM
21(1)
2.4.3 CMOS Image Sensors
21(1)
2.5 Lower Cost
22(1)
2.6 Application Based Drivers
22(3)
2.6.1 Microprocessors
22(1)
2.6.2 Memory
22(1)
2.6.3 Sensors
23(1)
2.6.4 Fields Programmable Gate Arrays (FPGAs)
23(1)
References
23(2)
3 Overview of 3D Integration Process Technology
25(20)
Philip Garrou
Christopher Bower
3.1 3D Integration Terminology
25(3)
3.1.1 Through Silicon Vias (TSVs)
25(2)
3.1.2 Wafer Thinning
27(1)
3.1.3 Aligned Wafer/IC Bonding
28(1)
3.2 Processing Sequences
28(6)
3.3 Technologies for 3D Integration
34(11)
3.3.1 TSV Formation
34(4)
3.3.2 Temporary Bonding to Carrier Wafer
38(1)
3.3.3 Thinning
39(1)
3.3.4 Alignment/Bonding
40(3)
References
43(2)
I Through Silicon Via Fabrication
45(130)
4 Deep Reactive Ion Etching of Through Silicon Vias
47(46)
Fred Roozeboom
Michiel A. Blauw
Yann Lamy
Eric van Grunsven
Wouter Dekkers
Jan F. Verhoeven
Eric (F.) van den Heuvel
Emile van der Drift
Erwin (W.M.M.) Kessels
Richard (M.C.M.) van de Sanden
4.1 Introduction
47(7)
4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects
47(1)
4.1.2 State of the Art and Basic Principles in DRIE
48(1)
4.1.3 Bosch Process
49(1)
4.1.4 Alternatives for Via Hole Creation
50(4)
4.2 DRIE Equipment and Characterization
54(8)
4.2.1 High-Density Plasma Reactors
54(5)
4.2.2 Plasma Chemistry
59(1)
4.2.3 Plasma Diagnostics and Surface Analysis
60(2)
4.3 DRIE Processing
62(16)
4.3.1 Mask Issues
62(4)
4.3.2 High Aspect Ratio Features
66(5)
4.3.3 Sidewall Passivation, Depassivation and Profile Control
71(7)
4.4 Practical Solutions in Via Etching
78(8)
4.4.1 Undercut and Scallop Reduction
79(1)
4.4.2 Sidewall Roughness Minimization
79(1)
4.4.3 Loading Effects
80(3)
4.4.4 Notching at Dielectric Interfaces
83(1)
4.4.5 Inspection of Via Structures
83(2)
4.4.6 In Situ Trench Depth Measurement
85(1)
4.5 Concluding Remarks
86(7)
Appendix A Glossary of Abbreviations
87(1)
Appendix B Examples of DRIE Recipes
88(1)
References
89(4)
5 Laser Ablation
93(14)
Wei-Chung Lo
S.M. Chang
5.1 Introduction
93(1)
5.2 Laser Technology for 3D Packaging
94(1)
5.2.1 Advantages
94(1)
5.2.2 Disadvantages
94(1)
5.3 For Si Substrate
94(6)
5.3.1 Difficulties
94(1)
5.3.2 Results
95(5)
5.4 Results for 3D Chip Stacking
100(3)
5.5 Reliabilities
103(1)
5.6 The Future
104(3)
References
105(2)
6 SiO2
107(14)
Robert Wieland
6.1 Introduction
107(1)
6.2 Dielectric CVD
107(8)
6.2.1 Sub-Atmospheric CVD
109(2)
6.2.2 Process Sequence of O3-Activated SACVD Deposition
111(1)
6.2.3 Conformal SACVD O3 TEOS Films for 3D Integration
111(4)
6.3 Dielectric Film Properties
115(1)
6.4 3D-Specifics Regarding SiO2 Dielectrics
116(3)
6.4.1 Wafer Pre-Processing
116(1)
6.4.2 Backside Processing Requirements on SiO2 Film Conformality in TSVs
117(1)
6.4.3 SiO2 Film Deposition on Thinned Silicon Substrates
118(1)
6.5 Concluding Remarks
119(2)
References
119(2)
7 Insulation -- Organic Dielectrics
121(12)
Philip Garrou
Christopher Bower
7.1 Parylene
121(4)
7.1.1 Parylene in TSVs
122(3)
7.1.2 Limiting Aspects of Parylene
125(1)
7.2 Plasma-Polymerized BCB
125(1)
7.3 Spray-Coated Organic Insulators
126(2)
7.4 Laser-Drilled Organics
128(2)
7.5 Concluding Remarks
130(3)
References
130(3)
8 Copper Plating
133(24)
Tom Ritzdorf
Rozalia Beica
Charles Sharbono
8.1 Introduction
133(1)
8.2 Copper Plating Equipment
134(1)
8.3 Copper Plating Processes
135(6)
8.3.1 Copper Lining
138(1)
8.3.2 Copper Full Fill With and Without Stud Formation
139(2)
8.4 Factors Affecting Copper Plating
141(3)
8.4.1 Via Profile and Smoothness
141(1)
8.4.2 Insulator/Barrier/Seed Layer Coverage
142(1)
8.4.3 Feature Wetting
143(1)
8.5 Plating Chemistries
144(2)
8.5.1 Acid Copper Sulfate Chemistry
144(1)
8.5.2 Methane Sulfonic Acid Chemistry
145(1)
8.5.3 Cyanide Chemistry
145(1)
8.5.4 Other Copper Plating Chemistries
145(1)
8.6 Plating Process Requirements
146(7)
8.6.1 Suggested Mechanisms for Superconformal Deposition
146(3)
8.6.2 Effect of Waveform and Current Density on Fill Performance
149(1)
8.6.3 Effect of Deposition Waveform on Fill Performance
150(1)
8.6.4 Impact of Feature Dimension on Fill Time
151(1)
8.6.5 Impact of Feature Dimension on Overburden
152(1)
8.6.6 Bath Analysis and Maintenance
153(1)
8.7 Summary
153(4)
References
154(3)
9 Metallization by Chemical Vapor Deposition of W and Cu
157(18)
Armin Klumpp
Robert Wieland
Ramona Ecke
Stefan E. Schulz
9.1 Introduction
157(1)
9.2 Commercial Precursors
158(3)
9.2.1 TiN Precursors
159(1)
9.2.2 Copper Precursors
159(1)
9.2.3 Tungsten Precursor
160(1)
9.3 Deposition Process Flow
161(8)
9.3.1 Barrier Deposition
162(1)
9.3.2 Adhesion Layer
163(2)
9.3.3 Copper Deposition
165(3)
9.3.4 Tungsten CVD Application to TSV Fill
168(1)
9.4 Complete TSV Metallization Including Filling and Etchback/CMP
169(3)
9.4.1 W-CVD Metallization
169(2)
9.4.2 Cu CVD Metallization
171(1)
9.5 Conclusions
172(3)
References
173(2)
II Wafer Thinning and Bonding Technology
175(96)
10 Fabrication, Processing and Singulation of Thin Wafers
177(32)
Werner Kroninger
10.1 Applications for Thin Silicon Dies
177(1)
10.2 Principal Facts: Thinning and Wafer Bow
177(2)
10.2.1 Where Does this Phenomenon Come From?
178(1)
10.3 Grinding and Thinning
179(4)
10.3.1 Grinding Parameters
180(1)
10.3.2 Vice Versa Influences of Parameters
181(2)
10.4 Stability and Flexibility
183(3)
10.4.1 Measuring Breaking-Strength and Flexibility
184(1)
10.4.2 Statistics and Evaluation
185(1)
10.5 Chip Thickness, Theoretical Model, Macroscopic Features
186(6)
10.5.1 Chip Thickness
186(1)
10.5.2 Theoretical Model
187(1)
10.5.3 Macroscopic Features: Chip Strength, Flexibility, Roughness and Hardness
188(3)
10.5.4 From Blank to Processed Chips: Changes?
191(1)
10.6 Stabilizing the Thin Wafer: Tapes and Carrier Systems
192(3)
10.6.1 Special Tapes for Handling Wafers and Dies
193(1)
10.6.2 Carrier Systems
193(2)
10.7 Separating the Chips: Dicing Influencing the Stability
195(11)
10.7.1 Classical Mechanical Dicing
195(4)
10.7.2 Laser Dicing
199(2)
10.7.3 Comparing Methods of Separation
201(5)
10.8 Conclusions
206(1)
10.9 Summary
206(3)
References
207(2)
11 Overview of Bonding Technologies for 3D Integration
209(14)
Jean-Pierre Joly
11.1 Introduction
209(1)
11.2 Direct Bonding
210(6)
11.2.1 Direct Bonding Principles
210(1)
11.2.2 Surface Direct SiO/SiO Bonding
211(4)
11.2.3 Metal Surface Activated Bonding
215(1)
11.3 Adhesive and Solder Bonding
216(3)
11.3.1 Polymer Bonding
217(1)
11.3.2 Metal Soldering or Eutectic Bonding
218(1)
11.4 Comparison of the Different Bonding Technologies
219(4)
References
221(2)
12 Chip-to-Wafer and Wafer-to-Wafer Integration Schemes
223(26)
Thorsten Matthias
Stefan Pargfrieder
Markus Wimplinger
Paul Lindner
12.1 Decision Criteria for 3D Integration
223(4)
12.1.1 Different Wafer Sizes
223(1)
12.1.2 Different Fabs
224(1)
12.1.3 Different Base Substrates
224(1)
12.1.4 Different Chip Size
224(1)
12.1.5 Number of Stacked Layers
224(1)
12.1.6 Modular Design
225(1)
12.1.7 Yield Issue
225(1)
12.1.8 Throughput
226(1)
12.1.9 Alignment
226(1)
12.1.10 Cost
226(1)
12.2 Enabling Technologies
227(17)
12.2.1 Aligned Wafer Bonding
227(6)
12.2.2 Bonding Methods
233(7)
12.2.3 Temporary Bonding/Debonding
240(2)
12.2.4 Chip to Wafer Bonding
242(2)
12.3 Integration Schemes for 3D Interconnect
244(4)
12.3.1 Face-to-Face Chip Stacking
244(1)
12.3.2 Face-to-Back Chip Stacking
245(3)
12.4 Conclusion
248(1)
References
248(1)
13 Polymer Adhesive Bonding Technology
249(12)
James Jian-Qiang Lu
Tim S. Cale
Ronald J. Gutmann
13.1 Polymer Adhesive Bonding Principle
249(1)
13.2 Polymer Adhesive Bonding Requirements and Materials
250(2)
13.3 Wafer Bonding Technology Using Polymer Adhesives
252(1)
13.4 Bonding Characterizations
253(5)
13.4.1 Optical Inspection Using Glass Wafer
255(1)
13.4.2 Bonding Strength Characterization Using Four-Point Bending
255(2)
13.4.3 Adhesive Wafer Bonding Integrity
257(1)
13.5 Conclusions
258(3)
References
258(3)
14 Bonding with Intermetallic Compounds
261(10)
Armin Klumpp
14.1 Introduction
261(1)
14.2 Technological Concepts
261(8)
14.2.1 Basic Material Selection
262(1)
14.2.2 Principal Processing Scheme
263(2)
14.2.3 Limiting Conditions for Applications
265(4)
14.3 Conclusion
269(2)
References
269(2)
III Integration Processes
271(246)
15 Commercial Activity
273(16)
Philip Garrou
15.1 Introduction
273(1)
15.2 Chip-on-Chip Activity
273(2)
15.3 Imaging Chips with TSV
275(1)
15.4 Memory
276(7)
15.5 Microprocessors & Misc. Applications
283(6)
16 Wafer-Level 3D System Integration
289(30)
Peter Ramm
M. Jurgen Wolf
Bernhard Wunderle
16.1 Introduction
289(2)
16.2 Wafer-Level 3D System Integration Technologies
291(17)
16.3 Reliability Issues
308(6)
16.4 Conclusions
314(5)
17 Interconnect Process at the University of Arkansas
319(20)
Susan Burkett
Leonard Schaper
17.1 Introduction
319(2)
17.2 TSV Process Flow
321(9)
17.3 Chip Assembly
330(3)
17.4 System Integration
333(1)
17.5 Summary
334(5)
References
334(5)
18 Vertical Interconnection by ASET
339(36)
Kenji Takahashi
Kazumasa Tanida
18.1 Introduction
339(2)
18.2 Fabrication Process Overview
341(1)
18.3 Via Filling by Cu Electrodeposition
341(4)
18.4 Handling of Thin Wafer
345(3)
18.5 3D Chip Stacking
348(15)
18.6 Thermal Performance of Chip Stack Module
363(4)
18.7 Electric Performance of Vertical Interconnection
367(3)
18.8 Practical Application of Through-vias
370(1)
18.9 Conclusion
371(4)
19 3D Integration at CEA-LETI
375(18)
Barbara Charlet
Lea Di Cioccio
Patrick Leduc
David Henry
19.1 Introduction
375(1)
19.2 Circuit Transfer for Efficient Stacking in 3D Integration
375(1)
19.3 Non-Destructive Characterization of Stacked Layers
376(4)
19.4 Example of 3D Integration Application Developments
380(10)
19.5 Summary
390(3)
20 Lincoln Laboratory's 3D Circuit Integration Technology
393(20)
James Burns
Brian Aull
Robert Berger
Nisha Checka
Chang-Lee Chen
Chenson Chen
Pascale Gouker
Craig Keast
Jeffrey Knecht
Antonio Soares
Vyshnavi Suntharalingam
Brian Tyrrell
Keith Warner
Bruce Wheeler
Peter Wyatt
Donna Yost
20.1 Introduction
393(1)
20.2 Lincoln Laboratory's Wafer-Scale 3D Circuit Integration Technology
394(8)
20.3 Transferred FDSOI Transistor and Device Properties
402(4)
20.4 3D Circuit and Device Results
406(3)
20.5 Summary
409(4)
21 3D Integration Technologies at IMEC
413(18)
Eric Beyne
21.1 Introduction
413(2)
21.2 Key Requirements for 3D-Interconnect Technologies
415(3)
21.3 3D Technologies at IMEC
418(13)
22 Fabrication Using Copper Thermo-Compression Bonding at MIT
431(16)
Chuan Seng Tan
Andy Fan
Rafael Reif
22.1 Introduction
431(1)
22.2 Copper Thermo-Compression Bonding
431(3)
22.3 Process Flow
434(8)
22.4 Discussion
442(3)
22.5 Summary
445(2)
23 Rensselaer 3D Integration Processes
447(16)
James Jian-Qiang Lu
Tim S. Cale
Ronald J. Gutmann
23.1 Introduction
447(1)
23.2 Via-Last 3D Platform Using Adhesive Wafer Bonding and Cu Damascene Inter-Wafer Interconnect
447(2)
23.3 Via-Last 3D Platform Feasibility Demonstration: Via-Chain Structure with Key Unit Processes of Alignment, Bonding, Thinning and Inter-wafer Interconnection
449(2)
23.4 Via-First 3D Platform with Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers
451(2)
23.5 Via-First 3D Platform Feasibility Demonstration: Via-Chain Structure with Cu/BCB Redistribution Layers
453(1)
23.6 Unit Process Advancements
454(4)
23.7 Carbon Nanotube (CNT) Interconnect
458(2)
23.8 Summary
460(3)
24 3D Integration at Tezzaron Semiconductor Corporation
463(24)
Robert Patti
24.1 Introduction
463(1)
24.2 Copper Bonding
463(1)
24.3 Yield Issues
464(1)
24.4 Interconnect Density
465(1)
24.5 Process Requirements for 3D DRAM
466(1)
24.6 FaStack Process Overview
467(1)
24.7 Bonding Before Thinning
467(1)
24.8 Tezzaron's TSVs
467(5)
24.9 Stacking Process Flow Details (with SuperContacts)
472(1)
24.10 Stacking Process Flow with SuperVias
473(1)
24.11 Additional Stacking Process Issues
474(7)
24.12 Working 3D Devices
481(1)
24.13 Qualification Results
481(4)
24.14 FaStack Summary
485(1)
24.15 Abbreviations and Definitions
486(1)
25 3D Integration at Ziptronix, Inc.
487(18)
Paul Enquist
25.1 Introduction
487(2)
25.2 Direct Bonding
489(8)
25.3 Direct Bond Interconnect
497(4)
25.4 Process Cost and Supply Chain Considerations
501(4)
26 3D Integration ZyCube
505(12)
Makoto Motoyoshi
26.1 Introduction
505(1)
26.2 Current 3D-LSI--New CSP Device for Sensors
505(7)
26.3 Future 3D-LSI Technology
512(5)
IV Design, Performance, and Thermal Management
517(134)
27 Design for 3D Integration at North Carolina State University
519(10)
Paul D. Franzon
27.1 Why 3D?
519(2)
27.2 Interconnect-Driven Case Studies
521(4)
27.3 Computer-Aided Design
525(1)
27.4 Discussion
526(3)
28 Modeling Approaches and Design Methods for 3D System Design
529(46)
Peter Schneider
Gunter Elst
28.1 Introduction
529(1)
28.2 Modeling and Simulation
530(35)
28.3 Design Methods for 3D Integration
565(6)
28.4 Conclusions
571(4)
29 Multiproject Circuit Design and Layout in Lincoln Laboratory's 3D Technology
575(8)
James Burns
Robert Berger
Nisha Checka
Craig Keast
Brian Tyrrell
Bruce Wheeler
29.1 Introduction
575(1)
29.2 3D Design and Layout Practice
575(3)
29.3 Design and Submission Procedures
578(5)
30 Computer-Aided Design for 3D Circuits at the University of Minnesota
583(16)
Sachin S. Sapatnekar
30.1 Introduction
583(1)
30.2 Thermal Analysis of 3D Designs
584(2)
30.3 Thermally-Driven Placement and Routing of 3D Designs
586(8)
30.4 Power Grid Design in 3D
594(2)
30.5 Conclusion
596(3)
31 Electrical Performance of 3D Circuits
599(24)
Arne Heittmann
Ulrich Ramacher
31.1 Introduction
599(8)
31.2 3D Chip Stack Technology
607(6)
31.3 Electrical Performance of 3D Contacts
613(5)
31.4 Summary and Conclusion
618(5)
32 Testing of 3D Circuits
623(12)
T.M. Mak
32.1 Introduction
623(1)
32.2 Yield and 3D Integration
624(3)
32.3 Known Good Die (KGD)
627(2)
32.4 Wafer Stacking Versus Die Stacking
629(3)
32.5 Defect Tolerant and Fault Tolerant 3D Stacks
632(3)
33 Thermal Management of Vertically Integrated Packages
635(16)
Thomas Brunschwiler
Bruno Michel
33.1 Introduction
635(2)
33.2 Fundamentals of Heat Transfer
637(2)
33.3 Thermal-Packaging Modeling
639(1)
33.4 Metrology in Thermal Packaging
640(1)
33.5 Thermal Packaging Components
641(3)
33.6 Heat Removal in Vertically-Integrated Packages
644(7)
V Applications
651(96)
34 3D and Microprocessors
653(22)
Pat Morrow
Sriram Muthukumar
34.1 Introduction
653(1)
34.2 Design of 3D Microprocessor Systems
654(7)
34.3 Fabrication of 3D Microprocessor Systems
661(9)
34.4 Conclusions
670(5)
35 3D Memories
675(14)
Mark Tuttle
35.1 Introduction
675(1)
35.2 Applications
675(4)
35.3 Redistribution Layer
679(2)
35.4 Through Wafer Interconnect
681(3)
35.5 Stacking
684(2)
35.6 Additional Issues
686(2)
35.7 Future of 3D Memories
688(1)
36 3D Read-Out Integrated Circuits for Advanced Sensor Arrays
689(14)
Christopher Bower
36.1 Introduction
689(1)
36.2 Current Activity in 3D ROICs
690(10)
36.3 Conclusions
700(3)
37 Power Devices
703(20)
Marc de Samber
Eric van Grunsven
David Heyes
37.1 Introduction
703(1)
37.2 Wafer Level Packaging for Discrete Semiconductor Devices
704(1)
37.3 Packaging for PowerMOSFET Devices
704(3)
37.4 Chip Size Packaging of Vertical MOSFETs
707(4)
37.5 Metal TWI Process for Vertical MOSFETs
711(7)
37.6 Further Evaluation of the TWI MOSFET CSPs
718(2)
37.7 Outlook
720(3)
38 Wireless Sensor Systems -- The e-CUBES Project
723(24)
Adrian M. Ionescu
Eric Beyne
Tierry Hilt
Thomas Herndl
Pierre Nicole
Mihai Sanduleanu
Anton Sauer
Herbert Shea
Maaike Taklo
Co Van Veen
Josef Weber
Werner Weber
Jurgen M. Wolf
Peter Ramm
38.1 Introduction
723(2)
38.2 e-CUBES Concept
725(2)
38.3 Enabling 3D Integration Technologies
727(4)
38.4 e-CUBES GHz Radios
731(4)
38.5 e-CUBES Applications and Roadmap
735(10)
38.6 Conclusion
745(2)
Conclusions 747(2)
Phil Garrou
Christopher Bower
Peter Ramm
Index 749
Dr. Philip Garrou, from Microelectronic Consultants of North Carolina, specializes in thin film microelectronic materials and applications, prior to which he was Director of Technology and New Business Development for Dow Chemicals - Advanced Electronic Materials business. He is a fellow of IEEE and IMAPS, has served as Associate Editor of the IEEE Transactions on Advanced Packaging, has authored two microelectronics texts and is co-author of over 75 peer reviewed publications and book chapters.

Dr. Christopher Bower is currently a Technical Manager at Semprius Inc., Durham, NC, where he leads a group working on the assembly and wafer-level packaging of advanced multi-junction solar cells for concentrator photovoltaics (CPV). Previously he was a senior scientist at RTI International where he worked on multiple DARPA-funded 3D integration programs. Dr. Bower has authored or co-authored over fifty papers and holds four patents.

Dr. Peter Ramm is head of the department Device and 3D Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for process integration of innovative devices and heterogeneous systems with a specific focus on 3D integration technologies. Dr. Ramm received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for over two decades on 3D integration technologies. Peter Ramm is author or co-author of over 100 publications and 24 patents. He received the 'Ashman Award 2009' from the International Electronics Packaging Society (IMAPS) 'For Pioneering Work on 3D IC Stacking and Integration, and leading-edge work on SiGe and Si technologies'. Peter Ramm is Fellow and Life Member of IMAPS, organizing committee and founding member of IEEE 3DIC conference and co-editor of Wiley's 'Handbook of Wafer Bonding'.