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ASIC and FPGA Verification: A Guide to Component Modeling [Pehme köide]

4.00/5 (2 hinnangut Goodreads-ist)
(CEO, Free Model Foundry)
  • Formaat: Paperback / softback, 336 pages, kõrgus x laius: 235x191 mm, kaal: 860 g, Illustrated; Illustrations
  • Sari: Systems on Silicon
  • Ilmumisaeg: 23-Oct-2004
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0125105819
  • ISBN-13: 9780125105811
Teised raamatud teemal:
ASIC and FPGA Verification: A Guide to Component ModelingSuurem pilt
  • Formaat: Paperback / softback, 336 pages, kõrgus x laius: 235x191 mm, kaal: 860 g, Illustrated; Illustrations
  • Sari: Systems on Silicon
  • Ilmumisaeg: 23-Oct-2004
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0125105819
  • ISBN-13: 9780125105811
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780125105811.html
Märksõnad:
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

Arvustused

Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possiblethe availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.

Randy Harr, Sevni Technology

This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.

Hardy Pottinger, University of Missouri-Rolla

Muu info

A valuable resource for anyone who needs to simulate digital designs not contained in a single chip.
Preface xv
PART I INTRODUCTION
1(32)
Introduction to Board-Level Verification
3(12)
Why Models are Needed
3(2)
Prototyping
3(1)
Simulation
4(1)
Definition of a Model
5(5)
Levels of Abstraction
6(1)
Model Types
7(2)
Technology-Independent Models
9(1)
Design Methods and Models
10(1)
How Models Fit in the FPGA/ASIC Design Flow
10(3)
The Design/Verification Flow
11(2)
Where to Get Models
13(1)
Summary
14(1)
Tour of a Simple Model
15(18)
Formatting
15(2)
Standard Interfaces
17(1)
Model Delays
18(1)
Vital Additions
19(6)
Vital Delay Types
19(1)
Vital Attributes
20(1)
Vital Primitive Call
21(1)
Vital Processes
22(2)
VitalPathDelays
24(1)
Interconnect Delays
25(2)
Finishing Touches
27(4)
Summary
31(2)
PART II RESOURCES AND STANDARDS
33(90)
VHDL Packages for Component Models
35(12)
STD_Logic_1164
35(2)
Type Declarations
36(1)
Functions
37(1)
Vital_Timing
37(2)
Declarations
37(1)
Procedures
38(1)
Vital_Primitives
39(2)
Declarations
40(1)
Functions and Procedures
40(1)
Vital_Memory
41(1)
Memory Functionality
41(1)
Memory Timing Specification
42(1)
Memory_Timing Checks
42(1)
FMF Packages
42(3)
FMF gen_utils and ecl_utils
43(1)
FMF ff_package
44(1)
FMF Conversions
45(1)
Summary
45(2)
An Introduction to SDF
47(12)
Overview of an SDF File
47(5)
Header
48(2)
Cell
50(1)
Timing Specifications
50(2)
SDF Capabilities
52(6)
Circuit Delays
52(3)
Timing Checks
55(3)
Summary
58(1)
Anatomy of a Vital Model
59(14)
Level 0 Guidelines
59(4)
Backannotation
60(1)
Timing Generics
60(1)
VitalDelayTypes
61(2)
Level 1 Guidelines
63(7)
Wire Delay Block
63(2)
Negative Constraint Block
65(1)
Processes
65(5)
Vital Primitives
70(1)
Concurrent Procedure Section
70(1)
Summary
70(3)
Modeling Delays
73(18)
Delay Types and Glitches
73(2)
Transport and Inertial Delays
73(1)
Glitches
74(1)
Distributed Delays
75(1)
Pin-to-Pin Delays
75(1)
Path Delay Procedures
76(6)
Using VPDs
82(1)
Generates and VPDs
83(1)
Device Delays
83(5)
Backannotating Path Delays
88(1)
Interconnect Delays
89(1)
Summary
90(1)
Vital Tables
91(16)
Advantages of Truth and State Tables
91(1)
Truth Tables
92(5)
Truth Table Construction
92(1)
Vital Table Symbols
92(1)
Truth Table Usage
93(4)
State Tables
97(3)
State Table Symbols
97(1)
State Table Construction
97(1)
State Table Usage
98(1)
State Table Algorithm
99(1)
Reducing Pessimism
100(1)
Memory Tables
101(4)
Memory Table Symbols
101(1)
Memory Table Construction
102(1)
Memory Table Usage
103(2)
Summary
105(2)
Timing Constraints
107(16)
The Purpose of Timing Constraint Checks
107(1)
Using Timing Constraint Checks in Vital Models
108(13)
Setup/Hold Checks
108(4)
Period/Pulsewidth Checks
112(2)
Recovery/Removal Checks
114(3)
Skew Checks
117(4)
Violations
121(1)
Summary
122(1)
PART III MODELING BASICS
123(66)
Modeling Components with Registers
125(22)
Anatomy of a Flip-Flop
125(12)
The Entity
125(4)
The Architecture
129(2)
A Vital Process
131(2)
Functionality Section
133(1)
Path Delay
134(1)
The ``B'' Side
135(2)
Anatomy of a Latch
137(9)
The Entity
138(2)
The Architecture
140(6)
Summary
146(1)
Conditional Delays and Timing Constraints
147(10)
Conditional Delays in Vital
147(2)
Conditional Delays in SDF
149(1)
Conditional Delay Alternatives
150(2)
Mapping SDF to Vital
152(1)
Conditional Timing Checks in Vital
153(3)
Summary
156(1)
Negative Timing Constraints
157(22)
How Negative Constraints Work
157(1)
Modeling Negative Constraints
158(18)
How Simulators Handle Negative Constraints
176(1)
Ramifications
177(1)
Summary
178(1)
Timing Files and Backannotation
179(10)
Anatomy of a Timing File
179(3)
Header
179(2)
Body
181(1)
FMFTIME
181(1)
Separate Timing Specifications
182(1)
Importing Timing Values
183(1)
Custom Timing Sections
183(1)
Generating Timing Files
184(1)
Generating SDF Files
184(1)
Backannotation and Hierarchy
185(2)
Summary
187(2)
PART IV ADVANCED MODELING
189(119)
Adding Timing to Your RTL Code
191(18)
Using Vital to Simulate Your RTL
191(1)
The Basic Wrapper
192(14)
A Wrapper for Verilog RTL
206(1)
Modeling Delays in Designs with Internal Clocks
206(1)
Caveats
207(1)
Summary
208(1)
Modeling Memories
209(42)
Memory Arrays
209(2)
The Shelor Method
210(1)
The Vital_Memory Package
210(1)
Modeling Memory Functionality
211(20)
Using the Behavioral (Shelor) Method
211(12)
Using the Vital2000 Method
223(8)
Vital_Memory Path Delays
231(1)
Vital_Memory Timing Constraints
232(3)
PreLoading Memories
235(3)
Behavioral Memory PreLoad
235(2)
Vital_Memory PreLoad
237(1)
Modeling Other Memory Types
238(11)
Synchronous Static RAM
238(3)
DRAM
241(3)
SDRAM
244(5)
Summary
249(2)
Considerations for Component Modeling
251(18)
Component Models and Netlisters
251(2)
File Contents
253(1)
Generics Passed from the Schematic
253(1)
Timing Generics
253(1)
Control Generics
253(1)
Integrating Models into a Schematic Capture System
254(2)
Library Structure
254(1)
Technology Independence
255(1)
Directories
255(1)
Map Files
256(1)
Using Models in the Design Process
256(6)
VHDL Libraries
257(1)
Schematic Entry
257(1)
Netlisting the Design
258(1)
VHDL Compilation
258(1)
SDF Generation
259(2)
Simulation
261(1)
Layout
261(1)
Signal Analysis
262(1)
Timing Backannotation
262(1)
Timing Analysis
262(1)
Special Considerations
262(4)
Schematic Considerations
262(1)
Model Considerations
263(3)
Summary
266(3)
Modeling Component-Centric Features
269(26)
Differential Inputs
269(10)
Bus Hold
279(3)
PLLs and DLLs
282(2)
Assertions
284(1)
Modifying Behavior with the TimingModel Generic
285(1)
State Machines
285(3)
Mixed Signal Devices
288(6)
Summary
294(1)
Testbenches for Component Models
295(13)
About Testbenches
295(1)
Tools
295(1)
Testbench Styles
296(1)
The Empty Testbench
296(1)
The Linear Testbench
296(1)
The Transactor Testbench
296(1)
Using Assertions
297(1)
Using Transactors
298(3)
Testing Memory Models
301(7)
Summary
308


By Richard Munden