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E-raamat: ASIC and FPGA Verification: A Guide to Component Modeling

4.00/5 (2 hinnangut Goodreads-ist)

Richard Munden (CEO, Free Model Foundry)

Formaat: PDF+DRM
Sari: Systems on Silicon
Ilmumisaeg: 23-Oct-2004
Kirjastus: Morgan Kaufmann Publishers In
Keel: eng
ISBN-13: 9780080475929

Teised raamatud teemal:

Computer architecture & logic design

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Formaat: PDF+DRM
Sari: Systems on Silicon
Ilmumisaeg: 23-Oct-2004
Kirjastus: Morgan Kaufmann Publishers In
Keel: eng
ISBN-13: 9780080475929

Teised raamatud teemal:

Computer architecture & logic design

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

Arvustused

Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possiblethe availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.

Randy Harr, Sevni Technology

This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.

Hardy Pottinger, University of Missouri-Rolla

Muu info

A valuable resource for anyone who needs to simulate digital designs not contained in a single chip.

Preface

PART I INTRODUCTION

(32)

Introduction to Board-Level Verification

(12)

Why Models are Needed

(2)

Prototyping

(1)

Simulation

(1)

Definition of a Model

(5)

Levels of Abstraction

(1)

Model Types

(2)

Technology-Independent Models

(1)

Design Methods and Models

(1)

How Models Fit in the FPGA/ASIC Design Flow

(3)

The Design/Verification Flow

(2)

Where to Get Models

(1)

Summary

(1)

Tour of a Simple Model

(18)

Formatting

(2)

Standard Interfaces

(1)

Model Delays

(1)

Vital Additions

(6)

Vital Delay Types

(1)

Vital Attributes

(1)

Vital Primitive Call

(1)

Vital Processes

(2)

VitalPathDelays

(1)

Interconnect Delays

(2)

Finishing Touches

(4)

Summary

(2)

PART II RESOURCES AND STANDARDS

(90)

VHDL Packages for Component Models

(12)

STD_Logic_1164

(2)

Type Declarations

(1)

Functions

(1)

Vital_Timing

(2)

Declarations

(1)

Procedures

(1)

Vital_Primitives

(2)

Declarations

(1)

Functions and Procedures

(1)

Vital_Memory

(1)

Memory Functionality

(1)

Memory Timing Specification

(1)

Memory_Timing Checks

(1)

FMF Packages

(3)

FMF gen_utils and ecl_utils

(1)

FMF ff_package

(1)

FMF Conversions

(1)

Summary

(2)

An Introduction to SDF

(12)

Overview of an SDF File

(5)

Header

(2)

Cell

(1)

Timing Specifications

(2)

SDF Capabilities

(6)

Circuit Delays

(3)

Timing Checks

(3)

Summary

(1)

Anatomy of a Vital Model

(14)

Level 0 Guidelines

(4)

Backannotation

(1)

Timing Generics

(1)

VitalDelayTypes

(2)

Level 1 Guidelines

(7)

Wire Delay Block

(2)

Negative Constraint Block

(1)

Processes

(5)

Vital Primitives

(1)

Concurrent Procedure Section

(1)

Summary

(3)

Modeling Delays

(18)

Delay Types and Glitches

(2)

Transport and Inertial Delays

(1)

Glitches

(1)

Distributed Delays

(1)

Pin-to-Pin Delays

(1)

Path Delay Procedures

(6)

Using VPDs

(1)

Generates and VPDs

(1)

Device Delays

(5)

Backannotating Path Delays

(1)

Interconnect Delays

(1)

Summary

(1)

Vital Tables

(16)

Advantages of Truth and State Tables

(1)

Truth Tables

(5)

Truth Table Construction

(1)

Vital Table Symbols

(1)

Truth Table Usage

(4)

State Tables

(3)

State Table Symbols

(1)

State Table Construction

(1)

State Table Usage

(1)

State Table Algorithm

(1)

Reducing Pessimism

100

(1)

Memory Tables

101

(4)

Memory Table Symbols

101

(1)

Memory Table Construction

102

(1)

Memory Table Usage

103

(2)

Summary

105

(2)

Timing Constraints

107

(16)

The Purpose of Timing Constraint Checks

107

(1)

Using Timing Constraint Checks in Vital Models

108

(13)

Setup/Hold Checks

108

(4)

Period/Pulsewidth Checks

112

(2)

Recovery/Removal Checks

114

(3)

Skew Checks

117

(4)

Violations

121

(1)

Summary

122

(1)

PART III MODELING BASICS

123

(66)

Modeling Components with Registers

125

(22)

Anatomy of a Flip-Flop

125

(12)

The Entity

125

(4)

The Architecture

129

(2)

A Vital Process

131

(2)

Functionality Section

133

(1)

Path Delay

134

(1)

The ``B'' Side

135

(2)

Anatomy of a Latch

137

(9)

The Entity

138

(2)

The Architecture

140

(6)

Summary

146

(1)

Conditional Delays and Timing Constraints

147

(10)

Conditional Delays in Vital

147

(2)

Conditional Delays in SDF

149

(1)

Conditional Delay Alternatives

150

(2)

Mapping SDF to Vital

152

(1)

Conditional Timing Checks in Vital

153

(3)

Summary

156

(1)

Negative Timing Constraints

157

(22)

How Negative Constraints Work

157

(1)

Modeling Negative Constraints

158

(18)

How Simulators Handle Negative Constraints

176

(1)

Ramifications

177

(1)

Summary

178

(1)

Timing Files and Backannotation

179

(10)

Anatomy of a Timing File

179

(3)

Header

179

(2)

Body

181

(1)

FMFTIME

181

(1)

Separate Timing Specifications

182

(1)

Importing Timing Values

183

(1)

Custom Timing Sections

183

(1)

Generating Timing Files

184

(1)

Generating SDF Files

184

(1)

Backannotation and Hierarchy

185

(2)

Summary

187

(2)

PART IV ADVANCED MODELING

189

(119)

Adding Timing to Your RTL Code

191

(18)

Using Vital to Simulate Your RTL

191

(1)

The Basic Wrapper

192

(14)

A Wrapper for Verilog RTL

206

(1)

Modeling Delays in Designs with Internal Clocks

206

(1)

Caveats

207

(1)

Summary

208

(1)

Modeling Memories

209

(42)

Memory Arrays

209

(2)

The Shelor Method

210

(1)

The Vital_Memory Package

210

(1)

Modeling Memory Functionality

211

(20)

Using the Behavioral (Shelor) Method

211

(12)

Using the Vital2000 Method

223

(8)

Vital_Memory Path Delays

231

(1)

Vital_Memory Timing Constraints

232

(3)

PreLoading Memories

235

(3)

Behavioral Memory PreLoad

235

(2)

Vital_Memory PreLoad

237

(1)

Modeling Other Memory Types

238

(11)

Synchronous Static RAM

238

(3)

DRAM

241

(3)

SDRAM

244

(5)

Summary

249

(2)

Considerations for Component Modeling

251

(18)

Component Models and Netlisters

251

(2)

File Contents

253

(1)

Generics Passed from the Schematic

253

(1)

Timing Generics

253

(1)

Control Generics

253

(1)

Integrating Models into a Schematic Capture System

254

(2)

Library Structure

254

(1)

Technology Independence

255

(1)

Directories

255

(1)

Map Files

256

(1)

Using Models in the Design Process

256

(6)

VHDL Libraries

257

(1)

Schematic Entry

257

(1)

Netlisting the Design

258

(1)

VHDL Compilation

258

(1)

SDF Generation

259

(2)

Simulation

261

(1)

Layout

261

(1)

Signal Analysis

262

(1)

Timing Backannotation

262

(1)

Timing Analysis

262

(1)

Special Considerations

262

(4)

Schematic Considerations

262

(1)

Model Considerations

263

(3)

Summary

266

(3)

Modeling Component-Centric Features

269

(26)

Differential Inputs

269

(10)

Bus Hold

279

(3)

PLLs and DLLs

282

(2)

Assertions

284

(1)

Modifying Behavior with the TimingModel Generic

285

(1)

State Machines

285

(3)

Mixed Signal Devices

288

(6)

Summary

294

(1)

Testbenches for Component Models

295

(13)

About Testbenches

295

(1)

Tools

295

(1)

Testbench Styles

296

(1)

The Empty Testbench

296

(1)

The Linear Testbench

296

(1)

The Transactor Testbench

296

(1)

Using Assertions

297

(1)

Using Transactors

298

(3)

Testing Memory Models

301

(7)

Summary

308

By Richard Munden

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Püsilink: https://www.kriso.ee/db/97800804759292e.html

Märksõnad:

Application specific integrated circuits

E-raamat: ASIC and FPGA Verification: A Guide to Component Modeling

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