List of abbreviations |
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xi | |
List of symbols |
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xiii | |
Preface |
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xvii | |
1 Introduction |
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1 | (6) |
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1.1 A/D conversion systems |
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1 | (4) |
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1.2 Motivation and objectives |
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5 | (1) |
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5 | (2) |
2 Accuracy, speed and power relation |
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7 | (14) |
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7 | (1) |
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2.2 IC-technology accuracy limitations |
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8 | (3) |
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8 | (2) |
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10 | (1) |
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2.2.3 Matching versus noise requirements |
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11 | (1) |
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11 | (2) |
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13 | (2) |
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2.5 CMOS technology trends |
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15 | (3) |
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18 | (3) |
3 AM converter architecture comparison |
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21 | (46) |
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21 | (1) |
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22 | (11) |
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23 | (3) |
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26 | (3) |
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29 | (4) |
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3.3 Folding and interpolation |
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33 | (5) |
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38 | (8) |
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46 | (8) |
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3.6 Successive approximation |
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54 | (2) |
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3.7 Theoretical power consumption comparison |
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56 | (10) |
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3.7.1 Figure-of-Merit (FoM) |
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57 | (1) |
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3.7.2 Architecture comparison as a function of the resolution |
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57 | (8) |
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3.7.3 Architecture comparison as a function of the sampling speed |
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65 | (1) |
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66 | (1) |
4 Enhancement techniques for two-step A/D converters |
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67 | (36) |
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67 | (1) |
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4.2 Error sources in a two-step architecture |
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67 | (2) |
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4.3 Residue gain in two-step A/D converters |
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69 | (6) |
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4.3.1 Single-residue signal processing |
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69 | (2) |
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4.3.2 Dual-residue signal processing |
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71 | (4) |
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75 | (1) |
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75 | (8) |
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75 | (1) |
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4.4.2 Calibration overview |
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75 | (7) |
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82 | (1) |
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4.5 Mixed-signal chopping and calibration |
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83 | (20) |
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4.5.1 Residue amplifier offset chopping |
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83 | (1) |
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4.5.2 Offset extraction from digital output |
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84 | (4) |
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4.5.3 Pseudo random chopping |
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88 | (3) |
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4.5.4 Offset extraction and analog compensation |
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91 | (2) |
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4.5.5 Offset extraction in a dual-residue two-step converter |
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93 | (9) |
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102 | (1) |
5 A 10-bit two-step ADC with analog online calibration |
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103 | (20) |
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103 | (2) |
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5.2 Two-Step architecture |
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105 | (5) |
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5.2.1 Coarse quantizer accuracy |
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106 | (1) |
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5.2.2 D/A converter and subtractor accuracy |
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107 | (1) |
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5.2.3 Coarse and fine A/D converter references |
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108 | (1) |
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5.2.4 Amplifier gain and offset accuracy |
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109 | (1) |
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110 | (7) |
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5.3.1 Track-and-hold circuit |
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111 | (1) |
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5.3.2 Coarse A/D, D/A converter and subtractor |
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111 | (1) |
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5.3.3 Coarse ladder requirements |
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112 | (1) |
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5.3.4 Offset compensated residue amplifier |
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113 | (1) |
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114 | (2) |
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116 | (1) |
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117 | (4) |
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121 | (1) |
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122 | (1) |
6 A 12-bit two-step ADC with mixed-signal chopping and calibration |
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123 | (26) |
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123 | (3) |
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6.2 Two-step architecture |
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126 | (7) |
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6.2.1 Interleaved sample-and-hold |
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127 | (1) |
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6.2.2 Coarse A/D converter |
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128 | (1) |
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6.2.3 Switching and residue signal generation |
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129 | (3) |
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132 | (1) |
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6.3 Mixed-signal chopping and calibration |
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133 | (3) |
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6.3.1 Residue amplifier offset |
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134 | (1) |
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134 | (1) |
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135 | (1) |
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136 | (5) |
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6.4.1 Interleaved sample-and-hold |
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136 | (1) |
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6.4.2 Coarse A/D converter |
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137 | (1) |
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6.4.3 Residue amplifier with offset compensating current D/A converter |
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138 | (1) |
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6.4.4 Folding-and-interpolating fine A/D converter |
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139 | (2) |
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141 | (4) |
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145 | (1) |
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146 | (3) |
7 A low-power 16-bit three-step ADC for imaging applications |
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149 | (20) |
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149 | (2) |
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7.2 Three-step architecture |
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151 | (5) |
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153 | (1) |
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7.2.2 Resolution distribution |
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154 | (1) |
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154 | (2) |
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156 | (2) |
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7.4 Mixed-signal chopping and calibration |
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158 | (3) |
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7.4.1 Mid and fine residue amplifier stage calibration |
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158 | (2) |
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160 | (1) |
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161 | (1) |
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162 | (5) |
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167 | (1) |
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168 | (1) |
8 Conclusions |
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169 | (4) |
A Static and dynamic accuracy requirements |
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173 | (4) |
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A.1 Static error requirments |
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173 | (2) |
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A.2 Dynamic error requirements |
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175 | (2) |
References |
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177 | (12) |
Index |
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189 | |