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E-raamat: Calibration Techniques in Nyquist A/D Converters

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In modern systems signal processing is performed in the digital domain. Contrary to analog circuits, digital signal processing offers more robustness, programmability, error correction and storage possibility. The trend to shift the A/D converter towards the input of the system requires A/D converters with more dynamic range and higher sampling speeds. This puts extreme demands on the A/D converter and potentially increases the power consumption.Calibration Techniques in Nyquist A/D Converters analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It is shown that in order to achieve high speed and high accuracy at high power efficiency, calibration is required. Calibration reduces the overall power consumption by using the available digital processing capability to relax the demands on critical power hungry analog components. Several calibration techniques are analyzed. The calibration techniques presented in this book are applicable to other analog-to-digital systems, such as those applied in integrated receivers. Further refinements will allow using analog components with less accuracy, which will then be compensated by digital signal processing. The presented methods allow implementing this without introducing a speed or power penalty.

This book analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It also provides an accessible overview of the state-of-the art in calibration techniques for Nyquist A/D converters. The calibration techniques presented are applicable to other analog-to-digital systems, such as those applied in integrated receivers. They allow implementation without introducing a speed or power penalty.
List of abbreviations xi
List of symbols xiii
Preface xvii
1 Introduction 1(6)
1.1 A/D conversion systems
1(4)
1.2 Motivation and objectives
5(1)
1.3 Layout of the book
5(2)
2 Accuracy, speed and power relation 7(14)
2.1 Introduction
7(1)
2.2 IC-technology accuracy limitations
8(3)
2.2.1 Process mismatch
8(2)
2.2.2 Thermal noise
10(1)
2.2.3 Matching versus noise requirements
11(1)
2.3 Speed and power
11(2)
2.4 Maximum speed
13(2)
2.5 CMOS technology trends
15(3)
2.6 Conclusions
18(3)
3 AM converter architecture comparison 21(46)
3.1 Introduction
21(1)
3.2 Flash
22(11)
3.2.1 Full flash
23(3)
3.2.2 Interpolation
26(3)
3.2.3 Averaging
29(4)
3.3 Folding and interpolation
33(5)
3.4 Two-step
38(8)
3.5 Pipe-line
46(8)
3.6 Successive approximation
54(2)
3.7 Theoretical power consumption comparison
56(10)
3.7.1 Figure-of-Merit (FoM)
57(1)
3.7.2 Architecture comparison as a function of the resolution
57(8)
3.7.3 Architecture comparison as a function of the sampling speed
65(1)
3.8 Conclusions
66(1)
4 Enhancement techniques for two-step A/D converters 67(36)
4.1 Introduction
67(1)
4.2 Error sources in a two-step architecture
67(2)
4.3 Residue gain in two-step A/D converters
69(6)
4.3.1 Single-residue signal processing
69(2)
4.3.2 Dual-residue signal processing
71(4)
4.3.3 Conclusions
75(1)
4.4 Offset calibration
75(8)
4.4.1 Introduction
75(1)
4.4.2 Calibration overview
75(7)
4.4.3 Conclusions
82(1)
4.5 Mixed-signal chopping and calibration
83(20)
4.5.1 Residue amplifier offset chopping
83(1)
4.5.2 Offset extraction from digital output
84(4)
4.5.3 Pseudo random chopping
88(3)
4.5.4 Offset extraction and analog compensation
91(2)
4.5.5 Offset extraction in a dual-residue two-step converter
93(9)
4.5.6 Conclusions
102(1)
5 A 10-bit two-step ADC with analog online calibration 103(20)
5.1 Introduction
103(2)
5.2 Two-Step architecture
105(5)
5.2.1 Coarse quantizer accuracy
106(1)
5.2.2 D/A converter and subtractor accuracy
107(1)
5.2.3 Coarse and fine A/D converter references
108(1)
5.2.4 Amplifier gain and offset accuracy
109(1)
5.3 Circuit design
110(7)
5.3.1 Track-and-hold circuit
111(1)
5.3.2 Coarse A/D, D/A converter and subtractor
111(1)
5.3.3 Coarse ladder requirements
112(1)
5.3.4 Offset compensated residue amplifier
113(1)
5.3.5 Fine A/D converter
114(2)
5.3.6 Timing
116(1)
5.4 Experimental results
117(4)
5.5 Discussion
121(1)
5.6 Conclusions
122(1)
6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123(26)
6.1 Introduction
123(3)
6.2 Two-step architecture
126(7)
6.2.1 Interleaved sample-and-hold
127(1)
6.2.2 Coarse A/D converter
128(1)
6.2.3 Switching and residue signal generation
129(3)
6.2.4 Residue amplifiers
132(1)
6.3 Mixed-signal chopping and calibration
133(3)
6.3.1 Residue amplifier offset
134(1)
6.3.2 Chopping
134(1)
6.3.3 Digital extraction
135(1)
6.4 Circuit design
136(5)
6.4.1 Interleaved sample-and-hold
136(1)
6.4.2 Coarse A/D converter
137(1)
6.4.3 Residue amplifier with offset compensating current D/A converter
138(1)
6.4.4 Folding-and-interpolating fine A/D converter
139(2)
6.5 Experimental results
141(4)
6.6 Discussion
145(1)
6.7 Conclusions
146(3)
7 A low-power 16-bit three-step ADC for imaging applications 149(20)
7.1 Introduction
149(2)
7.2 Three-step architecture
151(5)
7.2.1 Sample-and-hold
153(1)
7.2.2 Resolution distribution
154(1)
7.2.3 Switching
154(2)
7.3 Noise considerations
156(2)
7.4 Mixed-signal chopping and calibration
158(3)
7.4.1 Mid and fine residue amplifier stage calibration
158(2)
7.4.2 Quick calibration
160(1)
7.5 Supply voltages
161(1)
7.6 Experimental results
162(5)
7.7 Discussion
167(1)
7.8 Conclusions
168(1)
8 Conclusions 169(4)
A Static and dynamic accuracy requirements 173(4)
A.1 Static error requirments
173(2)
A.2 Dynamic error requirements
175(2)
References 177(12)
Index 189