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Circuit Design for Reliability 2015 ed. [Kõva köide]

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  • Formaat: Hardback, 272 pages, kõrgus x laius: 235x155 mm, kaal: 604 g, 132 Illustrations, color; 58 Illustrations, black and white; VI, 272 p. 190 illus., 132 illus. in color., 1 Hardback
  • Ilmumisaeg: 08-Nov-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461440777
  • ISBN-13: 9781461440772
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  • Formaat: Hardback, 272 pages, kõrgus x laius: 235x155 mm, kaal: 604 g, 132 Illustrations, color; 58 Illustrations, black and white; VI, 272 p. 190 illus., 132 illus. in color., 1 Hardback
  • Ilmumisaeg: 08-Nov-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461440777
  • ISBN-13: 9781461440772

Describing practical modeling and characterization techniques for designing reliable electrical circuits, this volume includes a thorough presentation of robust designs for major VLSI units. Its first-principle simulations aid physical understanding.



This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.
1 Introduction
1(4)
Ricardo Reis
Yu Cao
Gilson Wirth
2 Recent Trends in Bias Temperature Instability
5(16)
B. Kaczer
T. Grasser
J. Franco
M. Toledano-Luque
J. Roussel
M. Cho
E. Simoen
G. Groeseneken
3 Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability
21(26)
Gilson Wirth
Roberto da Silva
4 Atomistic Simulations on Reliability
47(22)
Dragica Vasileska
Nabil Ashraf
5 On-Chip Characterization of Statistical Device Degradation
69(24)
Takashi Sato
Hiromitsu Awano
6 Compact Modeling of BTI for Circuit Reliability Analysis
93(28)
Ketul B. Sutaria
Jyothi B. Velamala
Athul Ramkumar
Yu Cao
7 Circuit Resilience Roadmap
121(24)
Veit B. Kleeberger
Christian Weis
Ulf Schlichtmann
Norbert When
8 Layout Aware Electromigration Analysis of Power/Ground Networks
145(30)
Di-an Li
Malgorzata Marek-Sadowska
Sani R. Nassif
9 Power-Gating for Leakage Control and Beyond
175(32)
Andrea Calimera
Alberto Macii
Enrico Macii
Massimo Poncino
10 Soft Error Rate and Fault Tolerance Techniques for FPGAs
207(16)
Fernanda Kastensmidt
Ricardo Reis
11 Low Power Robust FinFET-Based SRAM Design in Scaled Technologies
223(32)
Sumeet Kumar Gupta
Kaushik Roy
12 Variability-Aware Clock Design
255
Matthew R. Guthaus
Gustavo Wilke