Preface |
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xv | |
Content overview |
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xvii | |
Feedback |
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xx | |
Acknowledgments |
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xx | |
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xxiii | |
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li | |
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1 Mixed-Signal Integrated Systems: Limitations and Challenges |
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1 | (10) |
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1.1 Integrated circuit design flow |
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2 | (4) |
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1.2 Design technique issues |
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6 | (1) |
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1.3 Integrated system perspectives |
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7 | (1) |
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1.4 Built-in self-test structures |
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8 | (1) |
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9 | (1) |
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9 | (2) |
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11 | (28) |
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12 | (11) |
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2.1.1 I/V characteristics of MOS transistors |
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13 | (1) |
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2.1.2 Drain current in the strong inversion approximation |
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14 | (3) |
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2.1.3 Drain current in the subthreshold region |
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17 | (3) |
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2.1.4 MOS transistor capacitances |
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20 | (1) |
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2.1.5 Scaling effects on MOS transistors |
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21 | (2) |
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2.2 Transistor SPICE models |
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23 | (8) |
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2.2.1 Electrical characteristics |
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23 | (4) |
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2.2.2 Temperature effects |
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27 | (1) |
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28 | (3) |
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31 | (1) |
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2.4 Circuit design assessment |
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32 | (5) |
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37 | (2) |
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3 Physical Design of MOS Integrated Circuits |
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39 | (20) |
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40 | (1) |
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41 | (5) |
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42 | (1) |
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43 | (1) |
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44 | (2) |
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3.3 Integrated-circuit (IC) interconnects |
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46 | (2) |
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3.4 Physical design considerations |
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48 | (5) |
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53 | (1) |
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53 | (1) |
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3.7 Circuit design assessment |
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53 | (4) |
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57 | (2) |
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4 Bias and Current Reference Circuits |
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59 | (36) |
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60 | (16) |
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4.1.1 Simple current mirror |
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60 | (2) |
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4.1.2 Cascode current mirror |
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62 | (13) |
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4.1.3 Low-voltage active current mirror |
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75 | (1) |
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4.2 Current and voltage references |
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76 | (11) |
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4.2.1 Supply-voltage independent current reference |
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78 | (1) |
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79 | (3) |
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4.2.2.1 Low-voltage bandgap voltage reference |
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82 | (1) |
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4.2.2.2 Curvature-compensated bandgap voltage reference |
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83 | (3) |
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4.2.3 Floating-gate voltage reference |
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86 | (1) |
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87 | (1) |
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4.4 Circuit design assessment |
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87 | (8) |
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93 | (2) |
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95 | (130) |
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5.1 Differential amplifier |
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96 | (18) |
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97 | (2) |
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5.1.2 Source-coupled differential transistor pair |
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99 | (2) |
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101 | (1) |
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5.1.4 Slew-rate limitation |
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102 | (1) |
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5.1.5 Small-signal characteristics |
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103 | (5) |
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108 | (2) |
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5.1.7 Noise in a differential transistor pair |
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110 | (1) |
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5.1.8 Operational amplifier |
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111 | (3) |
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5.2 Linearization techniques for transconductors |
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114 | (15) |
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5.3 Single-stage amplifier |
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129 | (1) |
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5.4 Folded-cascode amplifier |
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130 | (5) |
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5.5 Fully differential amplifier architectures |
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135 | (21) |
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5.5.1 Fully differential folded-cascode amplifier |
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135 | (1) |
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135 | (3) |
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5.5.1.2 Gain-enhanced structure |
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138 | (5) |
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5.5.2 Telescopic amplifier |
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143 | (3) |
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5.5.3 Common-mode feedback circuits |
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146 | (1) |
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5.5.3.1 Continuous-time common-mode feedback circuit |
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146 | (4) |
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5.5.3.2 Switched-capacitor common-mode feedback circuit |
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150 | (4) |
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5.5.4 Pseudo fully differential amplifier |
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154 | (2) |
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5.6 Multi-stage amplifier structures |
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156 | (30) |
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157 | (10) |
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5.6.2 Two-stage amplifier |
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167 | (7) |
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5.6.3 Optimization of a two-pole amplifier for fast settling response |
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174 | (3) |
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5.6.4 Three-stage amplifier |
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177 | (9) |
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5.7 Rail-to-rail amplifiers |
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186 | (8) |
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5.7.1 Amplifier with a class AB input stage |
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187 | (2) |
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5.7.2 Two-stage amplifier with class AB output stage |
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189 | (1) |
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5.7.3 Amplifier with rail-to-rail input and output stages |
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190 | (4) |
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5.8 Amplifier characterization |
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194 | (10) |
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5.8.1 Finite gain and bandwidth |
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194 | (1) |
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195 | (1) |
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5.8.3 Input and output impedances |
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195 | (1) |
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5.8.4 Power supply rejection |
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195 | (1) |
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195 | (1) |
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5.8.6 Low-frequency noise and dc offset voltage |
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196 | (2) |
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5.8.6.1 Auto-zero compensation scheme |
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198 | (3) |
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5.8.6.2 Chopper technique |
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201 | (3) |
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204 | (1) |
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5.10 Circuit design assessment |
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204 | (21) |
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219 | (6) |
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6 Nonlinear Analog Components |
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225 | (44) |
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226 | (16) |
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6.1.1 Amplifier-based comparator |
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226 | (7) |
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6.1.2 Comparator using charge balancing techniques |
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233 | (1) |
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6.1.3 Latched comparators |
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234 | (1) |
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6.1.3.1 Static comparator |
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235 | (4) |
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6.1.3.2 Dynamic comparator |
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239 | (3) |
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242 | (17) |
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244 | (1) |
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6.2.1.1 Multiplier core based on externally controlled transconductances |
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244 | (5) |
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6.2.1.2 Multiplier core based on the quarter-square technique |
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249 | (6) |
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255 | (1) |
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256 | (3) |
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259 | (1) |
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6.4 Circuit design assessment |
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259 | (10) |
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265 | (4) |
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7 Continuous-Time Circuits |
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269 | (134) |
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7.1 Wireless communication system |
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270 | (54) |
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7.1.1 Receiver and transmitter architectures |
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272 | (3) |
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7.1.2 Frequency translation and quadrature multiplexing |
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275 | (6) |
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7.1.3 Architecture of a harmonic-rejection transceiver |
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281 | (1) |
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282 | (1) |
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283 | (9) |
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7.1.4.2 Low-noise amplifier |
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292 | (10) |
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302 | (4) |
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7.1.6 Voltage-controlled oscillator |
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306 | (15) |
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7.1.7 Automatic gain control |
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321 | (3) |
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7.2 Continuous-time filters |
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324 | (13) |
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326 | (1) |
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327 | (3) |
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330 | (1) |
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7.2.4 gm-C operational amplifier (OA) circuits |
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331 | (4) |
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335 | (1) |
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336 | (1) |
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7.3 Filter characterization |
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337 | (1) |
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7.4 Filter design methods |
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338 | (18) |
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7.4.1 First-order filter design |
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340 | (2) |
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7.4.2 Biquadratic filter design methods |
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342 | (1) |
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7.4.2.1 Signal-flow graph-based design |
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342 | (4) |
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7.4.2.2 Gyrator-based design |
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346 | (3) |
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7.4.3 Ladder filter design methods |
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349 | (1) |
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7.4.3.1 LC ladder network-based design |
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349 | (3) |
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7.4.3.2 Signal-flow graph-based design |
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352 | (4) |
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7.5 Design considerations for continuous-time filters |
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356 | (3) |
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7.5.1 Automatic on-chip tuning of continuous-time filters |
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356 | (2) |
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7.5.2 Nonideal integrator |
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358 | (1) |
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7.6 Frequency-control systems |
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359 | (6) |
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7.6.1 Phase-locked-loop-based technique |
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359 | (1) |
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7.6.1.1 Operation principle |
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359 | (1) |
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7.6.1.2 Architecture of the master: VCO or VCF |
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360 | (1) |
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361 | (1) |
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7.6.1.4 Implementation issues |
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362 | (1) |
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7.6.2 Charge comparison-based technique |
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363 | (2) |
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7.7 Quality-factor and bandwidth control systems |
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365 | (4) |
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7.7.1 Magnitude-locked-loop-based technique |
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365 | (1) |
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7.7.2 Envelope detection-based technique |
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366 | (3) |
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7.8 Practical design considerations |
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369 | (3) |
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7.9 Other tuning strategies |
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372 | (6) |
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7.9.1 Tuning scheme using an external resistor |
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372 | (1) |
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373 | (2) |
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7.9.3 Tuning scheme based on adaptive filter technique |
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375 | (3) |
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378 | (1) |
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7.11 Circuit design assessment |
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378 | (25) |
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395 | (8) |
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8 Switched-Capacitor Circuits |
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403 | (106) |
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404 | (2) |
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406 | (1) |
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407 | (7) |
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407 | (2) |
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8.3.2 Switch error sources |
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409 | (4) |
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8.3.3 Switch compensation techniques |
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413 | (1) |
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8.4 Programmable capacitor arrays |
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414 | (2) |
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8.5 Operational amplifiers |
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416 | (1) |
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8.6 Track-and-hold (T/H) and sample-and-hold (S/H) circuits |
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417 | (8) |
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8.7 Switched-capacitor (SC) circuit principle |
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425 | (5) |
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430 | (11) |
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432 | (1) |
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433 | (8) |
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441 | (1) |
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8.9 SC ladder filter based on the LDI transform |
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441 | (8) |
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8.10 SC ladder filter based on the bilinear transform |
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449 | (10) |
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8.10.1 RLC filter prototype-based design |
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449 | (7) |
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8.10.2 Transfer function-based design of allpass filters |
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456 | (3) |
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8.11 Effects of the amplifier finite gain and bandwidth |
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459 | (7) |
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461 | (2) |
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8.11.2 Amplifier finite bandwidth |
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463 | (1) |
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8.11.2.1 Inverting integrator |
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463 | (2) |
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8.11.2.2 Noninverting integrator |
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465 | (1) |
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8.12 Settling time in the integrator |
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466 | (3) |
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8.13 Amplifier dc offset voltage limitations |
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469 | (1) |
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8.14 Computer-aided analysis of SC circuits |
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469 | (4) |
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8.15 T/H and S/H circuits based on SC circuit principle |
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473 | (5) |
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8.16 Circuit structures with low sensitivity to nonidealities |
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478 | (11) |
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479 | (6) |
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485 | (4) |
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8.17 Low-voltage SC circuits |
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489 | (3) |
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492 | (1) |
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8.19 Circuit design assessment |
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493 | (16) |
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503 | (6) |
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9 Data Converter Principles |
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509 | (24) |
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512 | (4) |
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513 | (2) |
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515 | (1) |
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516 | (1) |
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9.2 Data converter characterization |
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516 | (13) |
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9.2.1 Quantization errors |
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516 | (5) |
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9.2.2 Errors related to circuit components |
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521 | (2) |
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523 | (3) |
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526 | (3) |
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529 | (4) |
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531 | (2) |
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10 Nyquist Digital-to-Analog Converters |
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533 | (40) |
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10.1 Digital-to-analog converter (DAC) architectures |
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534 | (1) |
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10.1.1 Binary-weighted structure |
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534 | (1) |
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10.1.2 Thermometer-coded structure |
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534 | (1) |
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10.1.3 Segmented architecture |
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535 | (1) |
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10.2 Voltage-scaling DACs |
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535 | (10) |
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10.2.1 Basic resistor-string DAC |
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535 | (6) |
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10.2.2 Intermeshed resistor-string DAC |
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541 | (1) |
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10.2.3 Two-stage resistor-string DAC |
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542 | (3) |
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10.3 Current-scaling DACs |
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545 | (9) |
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10.3.1 Binary-weighted resistor DAC |
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545 | (2) |
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547 | (1) |
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10.3.3 Switched-current DAC |
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547 | (7) |
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554 | (3) |
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557 | (5) |
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10.6 Configuring a unipolar DAC for the bipolar conversion |
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562 | (2) |
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564 | (1) |
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565 | (1) |
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10.9 Circuit design assessment |
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566 | (7) |
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571 | (2) |
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11 Nyquist Analog-to-Digital Converters |
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573 | (78) |
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11.1 Analog-to-digital converter (ADC) architectures |
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574 | (65) |
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11.1.1 Successive approximation register ADC |
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574 | (10) |
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584 | (8) |
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592 | (12) |
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604 | (3) |
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11.1.5 Folding and interpolating ADC |
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607 | (12) |
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619 | (1) |
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619 | (13) |
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632 | (3) |
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11.1.9 Time-interleaved ADC |
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635 | (4) |
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639 | (1) |
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11.3 Circuit design assessment |
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640 | (11) |
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647 | (4) |
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12 Delta-Sigma Data Converters |
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651 | (118) |
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12.1 Delta-sigma analog-to-digital converter |
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652 | (65) |
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12.1.1 Time domain behavior |
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653 | (2) |
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12.1.2 Linear model of a discrete-time modulator |
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655 | (2) |
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12.1.3 Modulator dynamic range |
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657 | (4) |
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12.1.4 Continuous-time modulator |
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661 | (3) |
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12.1.5 Lowpass delta-sigma modulator |
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664 | (1) |
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12.1.5.1 Single-stage modulator with a 1-bit quantizer |
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664 | (4) |
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668 | (1) |
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668 | (5) |
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12.1.5.4 Modulator architectures with a multi-bit quantizer |
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673 | (3) |
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12.1.5.5 Cascaded modulator |
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676 | (10) |
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12.1.5.6 Effect of the multi-bit DAC nonlinearity |
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686 | (1) |
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12.1.5.7 Quantization noise shaping and inter-stage coefficient scaling |
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686 | (2) |
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12.1.6 Bandpass delta-sigma modulator |
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688 | (1) |
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12.1.6.1 Single-loop bandpass delta-sigma modulator |
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688 | (1) |
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12.1.6.2 Cascaded bandpass delta-sigma modulator |
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689 | (1) |
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690 | (7) |
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697 | (20) |
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12.2 Delta-sigma digital-to-analog converter |
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717 | (12) |
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12.2.1 Interpolation filter |
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718 | (7) |
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725 | (4) |
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12.3 Nyquist DAC design issues |
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729 | (10) |
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12.3.1 Data-weighted averaging technique |
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730 | (1) |
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12.3.2 Element selection logic based on a tree structure and butterfly shuffler |
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|
731 | (3) |
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12.3.3 Vector feedback DEM DAC |
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734 | (5) |
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12.4 Data converter testing and characterization |
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739 | (6) |
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12.4.1 Histogram-based testing |
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740 | (2) |
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12.4.2 Spectral analysis method |
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742 | (2) |
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12.4.3 Walsh transform-based transfer function estimation |
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744 | (1) |
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12.4.4 Testing using sine-fit algorithms |
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744 | (1) |
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12.5 Delta-sigma modulator-based oscillator |
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745 | (3) |
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12.6 Digital signal processor interfacing with data converters |
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748 | (5) |
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12.6.1 Parallel interfacing |
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751 | (1) |
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12.6.2 Serial interfacing |
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752 | (1) |
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12.7 Built-in self-test structures for data converters |
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753 | (3) |
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12.8 Circuit design assessment |
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756 | (13) |
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765 | (4) |
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13 Circuits for Clock Signal Generation and Synchronization |
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|
769 | (52) |
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13.1 Generation of clock signals with nonoverlapping phases |
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770 | (3) |
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773 | (2) |
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773 | (1) |
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774 | (1) |
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13.3 Charge-pump PLL building blocks |
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775 | (17) |
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13.3.1 Phase and frequency detector |
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775 | (3) |
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778 | (1) |
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13.3.2.1 Linear phase detector |
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778 | (1) |
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13.3.2.2 Binary phase detector |
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779 | (1) |
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13.3.2.3 Half-rate phase detector |
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780 | (3) |
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13.3.3 Charge-pump circuit |
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783 | (3) |
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786 | (2) |
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13.3.5 Voltage-controlled oscillator |
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788 | (4) |
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792 | (13) |
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13.4.1 Frequency synthesizer |
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792 | (10) |
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13.4.2 Clock and data recovery |
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802 | (3) |
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805 | (2) |
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13.6 PLL with a built-in self-test structure |
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807 | (1) |
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808 | (2) |
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810 | (1) |
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13.9 Circuit design assessment |
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810 | (11) |
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817 | (4) |
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Appendix A Logic Building Blocks |
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|
821 | (16) |
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821 | (1) |
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|
821 | (1) |
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A.1.2 Exclusive-OR and equivalence operations |
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822 | (1) |
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A.2 Combinational logic circuits |
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822 | (5) |
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822 | (2) |
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A.2.2 CMOS implementation |
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|
824 | (3) |
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A.3 Sequential logic circuits |
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|
827 | (7) |
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A.3.1 Asynchronous SR latch |
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|
828 | (1) |
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A.3.2 Asynchronous S R latch |
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|
828 | (1) |
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|
829 | (1) |
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|
829 | (2) |
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A.3.5 CMOS implementation |
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|
831 | (3) |
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|
834 | (3) |
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Appendix B Transistor sizing in building blocks |
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837 | (18) |
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837 | (5) |
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842 | (9) |
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851 | (3) |
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854 | (1) |
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Appendix C Signal-Flow Graph |
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855 | (6) |
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856 | (1) |
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857 | (3) |
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|
860 | (1) |
Index |
|
861 | |