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E-raamat: CMOS Analog Integrated Circuits: High-Speed and Power-Efficient Design

(IEEE, Canada)
  • Formaat: 926 pages
  • Ilmumisaeg: 19-Dec-2017
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781439855003
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  • Formaat: 926 pages
  • Ilmumisaeg: 19-Dec-2017
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781439855003

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High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important trends in designing these analog circuits and provides a complete, in-depth examination of design techniques and circuit architectures, emphasizing practical aspects of integrated circuit implementation.

Focusing on designing and verifying analog integrated circuits, the author reviews design techniques for more complex components such as amplifiers, comparators, and multipliers. The book details all aspects, from specification to the final chip, of the development and implementation process of filters, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), and delay-locked loops (DLLs). It also describes different equivalent transistor models, design and fabrication considerations for high-density integrated circuits in deep-submicrometer process, circuit structures for the design of current mirrors and voltage references, topologies of suitable amplifiers, continuous-time and switched-capacitor circuits, modulator architectures, and approaches to improve linearity of Nyquist converters. The text addresses the architectures and performance limitation issues affecting circuit operation and provides conceptual and practical solutions to problems that can arise in the design process.

This reference provides balanced coverage of theoretical and practical issues that will allow the reader to design CMOS analog integrated circuits with improved electrical performance. The chapters contain easy-to-follow mathematical derivations of all equations and formulas, graphical plots, and open-ended design problems to help determine most suitable architecture for a given set of performance specifications. This comprehensive and illustrative text for the design and analysis of CMOS analog integrated circuits serves as a valuable resource for analog circuit designers and graduate students in electrical engineering.
Preface xv
Content overview xvii
Feedback xx
Acknowledgments xx
List of Figures
xxiii
List of Tables
li
1 Mixed-Signal Integrated Systems: Limitations and Challenges
1(10)
1.1 Integrated circuit design flow
2(4)
1.2 Design technique issues
6(1)
1.3 Integrated system perspectives
7(1)
1.4 Built-in self-test structures
8(1)
1.5 Concluding remarks
9(1)
1.6 To probe further
9(2)
2 MOS Transistors
11(28)
2.1 Transistor structure
12(11)
2.1.1 I/V characteristics of MOS transistors
13(1)
2.1.2 Drain current in the strong inversion approximation
14(3)
2.1.3 Drain current in the subthreshold region
17(3)
2.1.4 MOS transistor capacitances
20(1)
2.1.5 Scaling effects on MOS transistors
21(2)
2.2 Transistor SPICE models
23(8)
2.2.1 Electrical characteristics
23(4)
2.2.2 Temperature effects
27(1)
2.2.3 Noise models
28(3)
2.3 Summary
31(1)
2.4 Circuit design assessment
32(5)
Bibliography
37(2)
3 Physical Design of MOS Integrated Circuits
39(20)
3.1 MOS Transistors
40(1)
3.2 Passive components
41(5)
3.2.1 Capacitors
42(1)
3.2.2 Resistors
43(1)
3.2.3 Inductors
44(2)
3.3 Integrated-circuit (IC) interconnects
46(2)
3.4 Physical design considerations
48(5)
3.5 IC packaging
53(1)
3.6 Summary
53(1)
3.7 Circuit design assessment
53(4)
Bibliography
57(2)
4 Bias and Current Reference Circuits
59(36)
4.1 Current mirrors
60(16)
4.1.1 Simple current mirror
60(2)
4.1.2 Cascode current mirror
62(13)
4.1.3 Low-voltage active current mirror
75(1)
4.2 Current and voltage references
76(11)
4.2.1 Supply-voltage independent current reference
78(1)
4.2.2 Bandgap references
79(3)
4.2.2.1 Low-voltage bandgap voltage reference
82(1)
4.2.2.2 Curvature-compensated bandgap voltage reference
83(3)
4.2.3 Floating-gate voltage reference
86(1)
4.3 Summary
87(1)
4.4 Circuit design assessment
87(8)
Bibliography
93(2)
5 CMOS Amplifiers
95(130)
5.1 Differential amplifier
96(18)
5.1.1 Dynamic range
97(2)
5.1.2 Source-coupled differential transistor pair
99(2)
5.1.3 Current mirror
101(1)
5.1.4 Slew-rate limitation
102(1)
5.1.5 Small-signal characteristics
103(5)
5.1.6 Offset voltage
108(2)
5.1.7 Noise in a differential transistor pair
110(1)
5.1.8 Operational amplifier
111(3)
5.2 Linearization techniques for transconductors
114(15)
5.3 Single-stage amplifier
129(1)
5.4 Folded-cascode amplifier
130(5)
5.5 Fully differential amplifier architectures
135(21)
5.5.1 Fully differential folded-cascode amplifier
135(1)
5.5.1.1 Basic structure
135(3)
5.5.1.2 Gain-enhanced structure
138(5)
5.5.2 Telescopic amplifier
143(3)
5.5.3 Common-mode feedback circuits
146(1)
5.5.3.1 Continuous-time common-mode feedback circuit
146(4)
5.5.3.2 Switched-capacitor common-mode feedback circuit
150(4)
5.5.4 Pseudo fully differential amplifier
154(2)
5.6 Multi-stage amplifier structures
156(30)
5.6.1 Output stage
157(10)
5.6.2 Two-stage amplifier
167(7)
5.6.3 Optimization of a two-pole amplifier for fast settling response
174(3)
5.6.4 Three-stage amplifier
177(9)
5.7 Rail-to-rail amplifiers
186(8)
5.7.1 Amplifier with a class AB input stage
187(2)
5.7.2 Two-stage amplifier with class AB output stage
189(1)
5.7.3 Amplifier with rail-to-rail input and output stages
190(4)
5.8 Amplifier characterization
194(10)
5.8.1 Finite gain and bandwidth
194(1)
5.8.2 Phase margin
195(1)
5.8.3 Input and output impedances
195(1)
5.8.4 Power supply rejection
195(1)
5.8.5 Slew rate
195(1)
5.8.6 Low-frequency noise and dc offset voltage
196(2)
5.8.6.1 Auto-zero compensation scheme
198(3)
5.8.6.2 Chopper technique
201(3)
5.9 Summary
204(1)
5.10 Circuit design assessment
204(21)
Bibliography
219(6)
6 Nonlinear Analog Components
225(44)
6.1 Comparators
226(16)
6.1.1 Amplifier-based comparator
226(7)
6.1.2 Comparator using charge balancing techniques
233(1)
6.1.3 Latched comparators
234(1)
6.1.3.1 Static comparator
235(4)
6.1.3.2 Dynamic comparator
239(3)
6.2 Multipliers
242(17)
6.2.1 Multiplier cores
244(1)
6.2.1.1 Multiplier core based on externally controlled transconductances
244(5)
6.2.1.2 Multiplier core based on the quarter-square technique
249(6)
6.2.1.3 Design issues
255(1)
6.2.2 Design examples
256(3)
6.3 Summary
259(1)
6.4 Circuit design assessment
259(10)
Bibliography
265(4)
7 Continuous-Time Circuits
269(134)
7.1 Wireless communication system
270(54)
7.1.1 Receiver and transmitter architectures
272(3)
7.1.2 Frequency translation and quadrature multiplexing
275(6)
7.1.3 Architecture of a harmonic-rejection transceiver
281(1)
7.1.4 Amplifiers
282(1)
7.1.4.1 Power amplifier
283(9)
7.1.4.2 Low-noise amplifier
292(10)
7.1.5 Mixer
302(4)
7.1.6 Voltage-controlled oscillator
306(15)
7.1.7 Automatic gain control
321(3)
7.2 Continuous-time filters
324(13)
7.2.1 RC circuits
326(1)
7.2.2 MOSFET-C circuits
327(3)
7.2.3 gm-C circuits
330(1)
7.2.4 gm-C operational amplifier (OA) circuits
331(4)
7.2.5 Summer circuits
335(1)
7.2.6 Gyrator
336(1)
7.3 Filter characterization
337(1)
7.4 Filter design methods
338(18)
7.4.1 First-order filter design
340(2)
7.4.2 Biquadratic filter design methods
342(1)
7.4.2.1 Signal-flow graph-based design
342(4)
7.4.2.2 Gyrator-based design
346(3)
7.4.3 Ladder filter design methods
349(1)
7.4.3.1 LC ladder network-based design
349(3)
7.4.3.2 Signal-flow graph-based design
352(4)
7.5 Design considerations for continuous-time filters
356(3)
7.5.1 Automatic on-chip tuning of continuous-time filters
356(2)
7.5.2 Nonideal integrator
358(1)
7.6 Frequency-control systems
359(6)
7.6.1 Phase-locked-loop-based technique
359(1)
7.6.1.1 Operation principle
359(1)
7.6.1.2 Architecture of the master: VCO or VCF
360(1)
7.6.1.3 Phase detector
361(1)
7.6.1.4 Implementation issues
362(1)
7.6.2 Charge comparison-based technique
363(2)
7.7 Quality-factor and bandwidth control systems
365(4)
7.7.1 Magnitude-locked-loop-based technique
365(1)
7.7.2 Envelope detection-based technique
366(3)
7.8 Practical design considerations
369(3)
7.9 Other tuning strategies
372(6)
7.9.1 Tuning scheme using an external resistor
372(1)
7.9.2 Self-tuned filter
373(2)
7.9.3 Tuning scheme based on adaptive filter technique
375(3)
7.10 Summary
378(1)
7.11 Circuit design assessment
378(25)
Bibliography
395(8)
8 Switched-Capacitor Circuits
403(106)
8.1 Anti-aliasing filter
404(2)
8.2 Capacitors
406(1)
8.3 Switches
407(7)
8.3.1 Switch description
407(2)
8.3.2 Switch error sources
409(4)
8.3.3 Switch compensation techniques
413(1)
8.4 Programmable capacitor arrays
414(2)
8.5 Operational amplifiers
416(1)
8.6 Track-and-hold (T/H) and sample-and-hold (S/H) circuits
417(8)
8.7 Switched-capacitor (SC) circuit principle
425(5)
8.8 SC filter design
430(11)
8.8.1 First-order filter
432(1)
8.8.2 Biquad filter
433(8)
8.8.3 Ladder filter
441(1)
8.9 SC ladder filter based on the LDI transform
441(8)
8.10 SC ladder filter based on the bilinear transform
449(10)
8.10.1 RLC filter prototype-based design
449(7)
8.10.2 Transfer function-based design of allpass filters
456(3)
8.11 Effects of the amplifier finite gain and bandwidth
459(7)
8.11.1 Amplifier dc gain
461(2)
8.11.2 Amplifier finite bandwidth
463(1)
8.11.2.1 Inverting integrator
463(2)
8.11.2.2 Noninverting integrator
465(1)
8.12 Settling time in the integrator
466(3)
8.13 Amplifier dc offset voltage limitations
469(1)
8.14 Computer-aided analysis of SC circuits
469(4)
8.15 T/H and S/H circuits based on SC circuit principle
473(5)
8.16 Circuit structures with low sensitivity to nonidealities
478(11)
8.16.1 Integrators
479(6)
8.16.2 Gain stages
485(4)
8.17 Low-voltage SC circuits
489(3)
8.18 Summary
492(1)
8.19 Circuit design assessment
493(16)
Bibliography
503(6)
9 Data Converter Principles
509(24)
9.1 Binary codes
512(4)
9.1.1 Unipolar codes
513(2)
9.1.2 Bipolar codes
515(1)
9.1.3 Remarks
516(1)
9.2 Data converter characterization
516(13)
9.2.1 Quantization errors
516(5)
9.2.2 Errors related to circuit components
521(2)
9.2.3 Static errors
523(3)
9.2.4 Dynamic errors
526(3)
9.3 Summary
529(4)
Bibliography
531(2)
10 Nyquist Digital-to-Analog Converters
533(40)
10.1 Digital-to-analog converter (DAC) architectures
534(1)
10.1.1 Binary-weighted structure
534(1)
10.1.2 Thermometer-coded structure
534(1)
10.1.3 Segmented architecture
535(1)
10.2 Voltage-scaling DACs
535(10)
10.2.1 Basic resistor-string DAC
535(6)
10.2.2 Intermeshed resistor-string DAC
541(1)
10.2.3 Two-stage resistor-string DAC
542(3)
10.3 Current-scaling DACs
545(9)
10.3.1 Binary-weighted resistor DAC
545(2)
10.3.2 R-2R ladder DAC
547(1)
10.3.3 Switched-current DAC
547(7)
10.4 Charge-scaling DAC
554(3)
10.5 Hybrid DAC
557(5)
10.6 Configuring a unipolar DAC for the bipolar conversion
562(2)
10.7 Algorithmic DAC
564(1)
10.8 Summary
565(1)
10.9 Circuit design assessment
566(7)
Bibliography
571(2)
11 Nyquist Analog-to-Digital Converters
573(78)
11.1 Analog-to-digital converter (ADC) architectures
574(65)
11.1.1 Successive approximation register ADC
574(10)
11.1.2 Integrating ADC
584(8)
11.1.3 Flash ADC
592(12)
11.1.4 Averaging ADC
604(3)
11.1.5 Folding and interpolating ADC
607(12)
11.1.6 Sub-ranging ADC
619(1)
11.1.7 Pipelined ADC
619(13)
11.1.8 Algorithmic ADC
632(3)
11.1.9 Time-interleaved ADC
635(4)
11.2 Summary
639(1)
11.3 Circuit design assessment
640(11)
Bibliography
647(4)
12 Delta-Sigma Data Converters
651(118)
12.1 Delta-sigma analog-to-digital converter
652(65)
12.1.1 Time domain behavior
653(2)
12.1.2 Linear model of a discrete-time modulator
655(2)
12.1.3 Modulator dynamic range
657(4)
12.1.4 Continuous-time modulator
661(3)
12.1.5 Lowpass delta-sigma modulator
664(1)
12.1.5.1 Single-stage modulator with a 1-bit quantizer
664(4)
12.1.5.2 Dithering
668(1)
12.1.5.3 Design examples
668(5)
12.1.5.4 Modulator architectures with a multi-bit quantizer
673(3)
12.1.5.5 Cascaded modulator
676(10)
12.1.5.6 Effect of the multi-bit DAC nonlinearity
686(1)
12.1.5.7 Quantization noise shaping and inter-stage coefficient scaling
686(2)
12.1.6 Bandpass delta-sigma modulator
688(1)
12.1.6.1 Single-loop bandpass delta-sigma modulator
688(1)
12.1.6.2 Cascaded bandpass delta-sigma modulator
689(1)
12.1.6.3 Design examples
690(7)
12.1.7 Decimation filter
697(20)
12.2 Delta-sigma digital-to-analog converter
717(12)
12.2.1 Interpolation filter
718(7)
12.2.2 Digital modulator
725(4)
12.3 Nyquist DAC design issues
729(10)
12.3.1 Data-weighted averaging technique
730(1)
12.3.2 Element selection logic based on a tree structure and butterfly shuffler
731(3)
12.3.3 Vector feedback DEM DAC
734(5)
12.4 Data converter testing and characterization
739(6)
12.4.1 Histogram-based testing
740(2)
12.4.2 Spectral analysis method
742(2)
12.4.3 Walsh transform-based transfer function estimation
744(1)
12.4.4 Testing using sine-fit algorithms
744(1)
12.5 Delta-sigma modulator-based oscillator
745(3)
12.6 Digital signal processor interfacing with data converters
748(5)
12.6.1 Parallel interfacing
751(1)
12.6.2 Serial interfacing
752(1)
12.7 Built-in self-test structures for data converters
753(3)
12.8 Circuit design assessment
756(13)
Bibliography
765(4)
13 Circuits for Clock Signal Generation and Synchronization
769(52)
13.1 Generation of clock signals with nonoverlapping phases
770(3)
13.2 Phase-locked loop
773(2)
13.2.1 PLL linear model
773(1)
13.2.2 Charge-pump PLL
774(1)
13.3 Charge-pump PLL building blocks
775(17)
13.3.1 Phase and frequency detector
775(3)
13.3.2 Phase detector
778(1)
13.3.2.1 Linear phase detector
778(1)
13.3.2.2 Binary phase detector
779(1)
13.3.2.3 Half-rate phase detector
780(3)
13.3.3 Charge-pump circuit
783(3)
13.3.4 Loop filter
786(2)
13.3.5 Voltage-controlled oscillator
788(4)
13.4 Applications
792(13)
13.4.1 Frequency synthesizer
792(10)
13.4.2 Clock and data recovery
802(3)
13.5 Delay-locked loop
805(2)
13.6 PLL with a built-in self-test structure
807(1)
13.7 PLL specifications
808(2)
13.8 Summary
810(1)
13.9 Circuit design assessment
810(11)
Bibliography
817(4)
Appendix A Logic Building Blocks
821(16)
A.1 Boolean algebra
821(1)
A.1.1 Basic operations
821(1)
A.1.2 Exclusive-OR and equivalence operations
822(1)
A.2 Combinational logic circuits
822(5)
A.2.1 Basic gates
822(2)
A.2.2 CMOS implementation
824(3)
A.3 Sequential logic circuits
827(7)
A.3.1 Asynchronous SR latch
828(1)
A.3.2 Asynchronous S R latch
828(1)
A.3.3 D latch
829(1)
A.3.4 D flip-flops
829(2)
A.3.5 CMOS implementation
831(3)
A.4 Bibliography
834(3)
Appendix B Transistor sizing in building blocks
837(18)
B.1 MOS transistor
837(5)
B.2 Amplifier
842(9)
B.3 Comparator and latch
851(3)
B.4 Bibliography
854(1)
Appendix C Signal-Flow Graph
855(6)
C.1 SFG reduction rules
856(1)
C.2 Mason's gain formula
857(3)
C.3 Bibliography
860(1)
Index 861
Tertulien Ndjountche is a senior member of the Institute of Electrical and Electronics Engineers (IEEE) and an member of Professional Engineer Ontario (PEO) in Gatineau, Canada.