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Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission 2014 ed. [Kõva köide]

  • Formaat: Hardback, 309 pages, kõrgus x laius: 235x155 mm, kaal: 6269 g, 3 Illustrations, color; 161 Illustrations, black and white; XXV, 309 p. 164 illus., 3 illus. in color., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 23-Jan-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319039245
  • ISBN-13: 9783319039244
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  • Formaat: Hardback, 309 pages, kõrgus x laius: 235x155 mm, kaal: 6269 g, 3 Illustrations, color; 161 Illustrations, black and white; XXV, 309 p. 164 illus., 3 illus. in color., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 23-Jan-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319039245
  • ISBN-13: 9783319039244
Teised raamatud teemal:
This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, eliminating all other analog components. Describes two chips designed using nanometer CMOS technologies.

This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components. After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware. As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling. The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality. Next, a high-level theoretical analysis of two different PWM-based architectures – baseband PWM and RF PWM – is made. On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits. Important design criteria are identified and different solutions are presented, along with their advantages and disadvantages. Finally, two chips designed in nanometer CMOS technologies are described, along with measurement results for validation.
1 Introduction
1(14)
1.1 Situation and Motivation
1(12)
1.1.1 Towards Software-Defined Radio
3(3)
1.1.2 Towards Fully Integrated CMOS Transceivers
6(1)
1.1.3 Switched-Mode Power Amplification
7(1)
1.1.4 Towards Fully Digital Transmitters
8(1)
1.1.5 The Bandpass Filter
9(1)
1.1.6 Frequency Range
10(1)
1.1.7 Continuous-Time Digital Circuits
10(2)
1.1.8 Summary
12(1)
1.2 Outline of this Book
13(2)
References
14(1)
2 Digital Transmitter Architectures: Overview
15(36)
2.1 Modulation
15(9)
2.1.1 Traditional Analog Modulation Schemes
16(1)
2.1.2 General Modulated Signal and Complex Representation
17(1)
2.1.3 Single-Carrier Digital Modulation Schemes
18(3)
2.1.4 OFDM
21(3)
2.1.5 Conclusion
24(1)
2.2 Power Amplifier
24(5)
2.2.1 Switched-Mode Power Amplifiers
24(4)
2.2.2 Differential PA and Power Combining
28(1)
2.3 Modulator Types
29(8)
2.3.1 Quadrature Modulator
29(3)
2.3.2 Polar Modulator
32(3)
2.3.3 Outphasing Modulator
35(2)
2.4 Types of 1-bit Coding
37(9)
2.4.1 Baseband Delta-Sigma Modulation
37(3)
2.4.2 Bandpass Delta-Sigma Modulation
40(1)
2.4.3 Baseband PWM
41(2)
2.4.4 RF PWM
43(2)
2.4.5 Other Coding Schemes
45(1)
2.4.6 Multibit Noise Shaping
45(1)
2.5 Conclusion
46(5)
References
47(4)
3 High-Level Analysis of Fully Digital PWM Transmitters
51(74)
3.1 Phase Modulation
52(10)
3.1.1 Ideal Phase Modulation
53(1)
3.1.2 Phase Modulation on Square Wave
54(2)
3.1.3 Effects of Quantization
56(2)
3.1.4 Effects of Sampling
58(2)
3.1.5 Complete PMC Spectrum
60(2)
3.2 General PWM Theory
62(6)
3.2.1 Definition of PWM
62(1)
3.2.2 Types of Pulse Width Modulators
63(1)
3.2.3 Expressions for PWM Signals and Spectra
64(4)
3.3 Trailing-Edge Baseband PWM
68(4)
3.3.1 Ideal Baseband PWM Spectrum
69(2)
3.3.2 Effects of Quantization
71(1)
3.3.3 Effects of Sampling
72(1)
3.4 Polar Transmitter with Baseband PWM
72(23)
3.4.1 Complete Signal Spectrum
72(4)
3.4.2 In-Band Noise Terms
76(4)
3.4.3 Out-of-Band Distortion Term
80(1)
3.4.4 Intermodulation Terms
80(8)
3.4.5 Summary
88(1)
3.4.6 Simulation Results
89(6)
3.5 Double-Edge RF PWM
95(13)
3.5.1 Trailing-Edge Versus Double-Edge RF PWM
96(3)
3.5.2 Required Transformations on the AM Signal
99(1)
3.5.3 Adding Phase Modulation
100(1)
3.5.4 Differential RF PWM
101(2)
3.5.5 Ideal RF PWM Spectrum
103(1)
3.5.6 Effects of Quantization
104(2)
3.5.7 Effects of Sampling
106(2)
3.6 Polar Transmitter with RF PWM
108(9)
3.6.1 Complete Signal Spectrum
108(1)
3.6.2 In-Band Noise Terms
109(2)
3.6.3 Out-of-Band Distortion Terms
111(1)
3.6.4 Summary
112(1)
3.6.5 Simulation Results
112(5)
3.7 Multilevel PWM
117(5)
3.7.1 Multilevel Baseband PWM
118(3)
3.7.2 Multilevel RF PWM
121(1)
3.8 Conclusion
122(3)
References
122(3)
4 Continuous-Time Digital Design Techniques
125(62)
4.1 Motivation and Comparison
125(2)
4.2 Applications of Continuous-Time Digital Circuits
127(5)
4.2.1 Time-to-Digital Conversion
127(2)
4.2.2 Digital-to-Time Conversion
129(2)
4.2.3 Applications of TDC and DTC Circuits
131(1)
4.3 Delay Lines
132(5)
4.3.1 The Inverter Chain
132(2)
4.3.2 Noninverting Delay Elements
134(1)
4.3.3 Differential Delay Elements
135(1)
4.3.4 Conclusion
136(1)
4.4 Achieving Sub-Gate-Delay Resolution
137(6)
4.4.1 Passive Delay Lines
137(1)
4.4.2 Resistive Interpolation
138(4)
4.4.3 Other Implementations for Sub-Gate-Delay Resolution
142(1)
4.5 Tuning the Unit Delay
143(3)
4.5.1 Supply Modulation
143(1)
4.5.2 Adding a Variable Load
144(1)
4.5.3 Adding Control Transistors
145(1)
4.5.4 Conclusion
146(1)
4.6 Ensuring Correct Delay
146(13)
4.6.1 Symmetry and Matching
147(1)
4.6.2 Global Process Variations and Locking
147(4)
4.6.3 Local Process Variations
151(6)
4.6.4 Pulse Swallowing and Pulse Shrinking
157(2)
4.7 Basic Building Blocks for Continuous-Time Digital Circuits
159(16)
4.7.1 Symmetrical NAND/NOR Gates
159(3)
4.7.2 Multiplexer-Based Gates
162(1)
4.7.3 XOR Gates
163(4)
4.7.4 Multiplexers
167(8)
4.8 Design Flow
175(8)
4.8.1 High-Level Matlab Model
176(4)
4.8.2 Transistor-Level Simulations
180(1)
4.8.3 Layout and Parasitic Extraction
181(1)
4.8.4 Remark: HDL Simulations
182(1)
4.9 Conclusion
183(4)
References
183(4)
5 A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA Based on Baseband PWM
187(32)
5.1 Architecture Overview
187(3)
5.2 Implementation
190(10)
5.2.1 Delay Elements
190(4)
5.2.2 Locking and Multistandard Support
194(2)
5.2.3 Multiplexers
196(2)
5.2.4 Symmetrical NAND and NOR Gates
198(1)
5.2.5 XOR Gates
198(1)
5.2.6 Layout
199(1)
5.3 Operating Modes and System Parameters
200(1)
5.4 Measurement Results
201(15)
5.4.1 Measurements on Transmitter Front-End
202(6)
5.4.2 Measurements with Power Amplifier
208(7)
5.4.3 Power Consumption
215(1)
5.5 Conclusion
216(3)
References
217(2)
6 A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D PAs Using Baseband and RF PWM
219(36)
6.1 Architecture Overview
219(5)
6.1.1 Baseband PWM System
219(1)
6.1.2 RF PWM System
220(3)
6.1.3 Combined System
223(1)
6.2 Implementation
224(9)
6.2.1 Delay Elements
226(2)
6.2.2 Locking Mechanism
228(2)
6.2.3 Multiplexers
230(1)
6.2.4 XOR Gates
231(1)
6.2.5 Single-Ended to Differential Conversion
231(1)
6.2.6 Signal and Clock Gating
232(1)
6.2.7 Layout
233(1)
6.3 Operating Modes and System Parameters
233(1)
6.4 Measurement Results
234(19)
6.4.1 Baseband PWM Front-End
234(7)
6.4.2 RF PWM Front-End
241(12)
6.5 Conclusion
253(2)
References
253(2)
7 Conclusions and Future Work
255(22)
7.1 Which Transmitter Architecture to Choose?
255(4)
7.2 Is Continuous-Time Digital Hardware Necessary?
259(2)
7.3 Comparison to State-of-the-Art
261(5)
7.4 Future Work
266(11)
7.4.1 Digital Transmitter Architectures
266(4)
7.4.2 Continuous-Time Building Blocks
270(3)
7.4.3 Design Flow
273(1)
7.4.4 Spectral Analysis
273(1)
References
273(4)
Appendix A Definitions, Conventions and Overview of Used Theory 277(20)
Appendix B Derivations and Considerations Regarding PWM 297(8)
Index 305