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1 | (14) |
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1.1 Situation and Motivation |
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1 | (12) |
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1.1.1 Towards Software-Defined Radio |
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3 | (3) |
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1.1.2 Towards Fully Integrated CMOS Transceivers |
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6 | (1) |
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1.1.3 Switched-Mode Power Amplification |
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7 | (1) |
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1.1.4 Towards Fully Digital Transmitters |
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8 | (1) |
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1.1.5 The Bandpass Filter |
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9 | (1) |
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10 | (1) |
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1.1.7 Continuous-Time Digital Circuits |
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10 | (2) |
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12 | (1) |
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13 | (2) |
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14 | (1) |
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2 Digital Transmitter Architectures: Overview |
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15 | (36) |
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15 | (9) |
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2.1.1 Traditional Analog Modulation Schemes |
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16 | (1) |
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2.1.2 General Modulated Signal and Complex Representation |
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17 | (1) |
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2.1.3 Single-Carrier Digital Modulation Schemes |
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18 | (3) |
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21 | (3) |
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24 | (1) |
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24 | (5) |
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2.2.1 Switched-Mode Power Amplifiers |
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24 | (4) |
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2.2.2 Differential PA and Power Combining |
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28 | (1) |
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29 | (8) |
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2.3.1 Quadrature Modulator |
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29 | (3) |
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32 | (3) |
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2.3.3 Outphasing Modulator |
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35 | (2) |
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2.4 Types of 1-bit Coding |
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37 | (9) |
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2.4.1 Baseband Delta-Sigma Modulation |
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37 | (3) |
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2.4.2 Bandpass Delta-Sigma Modulation |
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40 | (1) |
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41 | (2) |
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43 | (2) |
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2.4.5 Other Coding Schemes |
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45 | (1) |
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2.4.6 Multibit Noise Shaping |
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45 | (1) |
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46 | (5) |
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47 | (4) |
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3 High-Level Analysis of Fully Digital PWM Transmitters |
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51 | (74) |
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52 | (10) |
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3.1.1 Ideal Phase Modulation |
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53 | (1) |
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3.1.2 Phase Modulation on Square Wave |
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54 | (2) |
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3.1.3 Effects of Quantization |
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56 | (2) |
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3.1.4 Effects of Sampling |
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58 | (2) |
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3.1.5 Complete PMC Spectrum |
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60 | (2) |
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62 | (6) |
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62 | (1) |
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3.2.2 Types of Pulse Width Modulators |
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63 | (1) |
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3.2.3 Expressions for PWM Signals and Spectra |
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64 | (4) |
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3.3 Trailing-Edge Baseband PWM |
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68 | (4) |
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3.3.1 Ideal Baseband PWM Spectrum |
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69 | (2) |
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3.3.2 Effects of Quantization |
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71 | (1) |
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3.3.3 Effects of Sampling |
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72 | (1) |
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3.4 Polar Transmitter with Baseband PWM |
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72 | (23) |
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3.4.1 Complete Signal Spectrum |
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72 | (4) |
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3.4.2 In-Band Noise Terms |
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76 | (4) |
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3.4.3 Out-of-Band Distortion Term |
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80 | (1) |
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3.4.4 Intermodulation Terms |
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80 | (8) |
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88 | (1) |
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89 | (6) |
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95 | (13) |
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3.5.1 Trailing-Edge Versus Double-Edge RF PWM |
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96 | (3) |
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3.5.2 Required Transformations on the AM Signal |
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99 | (1) |
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3.5.3 Adding Phase Modulation |
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100 | (1) |
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3.5.4 Differential RF PWM |
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101 | (2) |
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3.5.5 Ideal RF PWM Spectrum |
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103 | (1) |
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3.5.6 Effects of Quantization |
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104 | (2) |
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3.5.7 Effects of Sampling |
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106 | (2) |
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3.6 Polar Transmitter with RF PWM |
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108 | (9) |
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3.6.1 Complete Signal Spectrum |
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108 | (1) |
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3.6.2 In-Band Noise Terms |
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109 | (2) |
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3.6.3 Out-of-Band Distortion Terms |
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111 | (1) |
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112 | (1) |
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112 | (5) |
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117 | (5) |
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3.7.1 Multilevel Baseband PWM |
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118 | (3) |
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121 | (1) |
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122 | (3) |
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122 | (3) |
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4 Continuous-Time Digital Design Techniques |
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125 | (62) |
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4.1 Motivation and Comparison |
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125 | (2) |
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4.2 Applications of Continuous-Time Digital Circuits |
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127 | (5) |
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4.2.1 Time-to-Digital Conversion |
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127 | (2) |
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4.2.2 Digital-to-Time Conversion |
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129 | (2) |
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4.2.3 Applications of TDC and DTC Circuits |
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131 | (1) |
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132 | (5) |
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132 | (2) |
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4.3.2 Noninverting Delay Elements |
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134 | (1) |
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4.3.3 Differential Delay Elements |
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135 | (1) |
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136 | (1) |
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4.4 Achieving Sub-Gate-Delay Resolution |
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137 | (6) |
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4.4.1 Passive Delay Lines |
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137 | (1) |
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4.4.2 Resistive Interpolation |
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138 | (4) |
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4.4.3 Other Implementations for Sub-Gate-Delay Resolution |
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142 | (1) |
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4.5 Tuning the Unit Delay |
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143 | (3) |
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143 | (1) |
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4.5.2 Adding a Variable Load |
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144 | (1) |
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4.5.3 Adding Control Transistors |
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145 | (1) |
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146 | (1) |
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4.6 Ensuring Correct Delay |
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146 | (13) |
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4.6.1 Symmetry and Matching |
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147 | (1) |
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4.6.2 Global Process Variations and Locking |
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147 | (4) |
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4.6.3 Local Process Variations |
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151 | (6) |
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4.6.4 Pulse Swallowing and Pulse Shrinking |
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157 | (2) |
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4.7 Basic Building Blocks for Continuous-Time Digital Circuits |
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159 | (16) |
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4.7.1 Symmetrical NAND/NOR Gates |
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159 | (3) |
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4.7.2 Multiplexer-Based Gates |
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162 | (1) |
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163 | (4) |
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167 | (8) |
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175 | (8) |
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4.8.1 High-Level Matlab Model |
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176 | (4) |
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4.8.2 Transistor-Level Simulations |
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180 | (1) |
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4.8.3 Layout and Parasitic Extraction |
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181 | (1) |
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4.8.4 Remark: HDL Simulations |
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182 | (1) |
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183 | (4) |
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183 | (4) |
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5 A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA Based on Baseband PWM |
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187 | (32) |
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5.1 Architecture Overview |
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187 | (3) |
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190 | (10) |
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190 | (4) |
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5.2.2 Locking and Multistandard Support |
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194 | (2) |
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196 | (2) |
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5.2.4 Symmetrical NAND and NOR Gates |
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198 | (1) |
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198 | (1) |
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199 | (1) |
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5.3 Operating Modes and System Parameters |
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200 | (1) |
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201 | (15) |
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5.4.1 Measurements on Transmitter Front-End |
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202 | (6) |
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5.4.2 Measurements with Power Amplifier |
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208 | (7) |
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215 | (1) |
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216 | (3) |
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217 | (2) |
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6 A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D PAs Using Baseband and RF PWM |
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219 | (36) |
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6.1 Architecture Overview |
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219 | (5) |
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6.1.1 Baseband PWM System |
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219 | (1) |
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220 | (3) |
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223 | (1) |
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224 | (9) |
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226 | (2) |
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228 | (2) |
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230 | (1) |
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231 | (1) |
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6.2.5 Single-Ended to Differential Conversion |
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231 | (1) |
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6.2.6 Signal and Clock Gating |
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232 | (1) |
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233 | (1) |
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6.3 Operating Modes and System Parameters |
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233 | (1) |
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234 | (19) |
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6.4.1 Baseband PWM Front-End |
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234 | (7) |
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241 | (12) |
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253 | (2) |
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253 | (2) |
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7 Conclusions and Future Work |
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255 | (22) |
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7.1 Which Transmitter Architecture to Choose? |
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255 | (4) |
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7.2 Is Continuous-Time Digital Hardware Necessary? |
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259 | (2) |
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7.3 Comparison to State-of-the-Art |
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261 | (5) |
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266 | (11) |
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7.4.1 Digital Transmitter Architectures |
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266 | (4) |
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7.4.2 Continuous-Time Building Blocks |
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270 | (3) |
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273 | (1) |
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273 | (1) |
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273 | (4) |
Appendix A Definitions, Conventions and Overview of Used Theory |
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277 | (20) |
Appendix B Derivations and Considerations Regarding PWM |
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297 | (8) |
Index |
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305 | |