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Embedded Memory Design for Multi-Core and Systems on Chip Softcover reprint of the original 1st ed. 2014 [Pehme köide]

  • Formaat: Paperback / softback, 95 pages, kõrgus x laius: 235x155 mm, kaal: 1825 g, 37 Illustrations, color; 26 Illustrations, black and white; XIII, 95 p. 63 illus., 37 illus. in color., 1 Paperback / softback
  • Sari: Analog Circuits and Signal Processing 116
  • Ilmumisaeg: 23-Aug-2016
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1493948016
  • ISBN-13: 9781493948017
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Embedded Memory Design for Multi-Core and Systems on Chip Softcover reprint of the original 1st ed. 2014Suurem pilt
  • Formaat: Paperback / softback, 95 pages, kõrgus x laius: 235x155 mm, kaal: 1825 g, 37 Illustrations, color; 26 Illustrations, black and white; XIII, 95 p. 63 illus., 37 illus. in color., 1 Paperback / softback
  • Sari: Analog Circuits and Signal Processing 116
  • Ilmumisaeg: 23-Aug-2016
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1493948016
  • ISBN-13: 9781493948017
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781493948017.html
Märksõnad:
This book describes the various tradeoffs systems designers face when designing embedded memory. It uses real product examples to demonstrate embedded memory design flow from architecture, to circuit design, design for test and yield analysis.

This book describes the various tradeoffs systems designers face when designing embedded memory. Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test. The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.
1 Introduction
1(12)
1.1 Embedded Memory Importance
1(1)
1.2 Embedded Memory Types
2(3)
1.2.1 Volatility
2(1)
1.2.2 Memory Cell Type
3(2)
1.3 Memory Implementation with Discrete Component
5(3)
1.4 Memory Implementation as an Array
8(1)
1.5 Memory Management
9(1)
1.6 Memory Hierarchy
9(4)
2 Cache Architecture and Main Blocks
13(16)
2.1 Cache Main Blocks and Data Flow
13(2)
2.2 Cache Associativity
15(1)
2.3 Cache Memory Write Policy
16(1)
2.3.1 Write-Through Policy
16(1)
2.3.2 Write-Back Policy
16(1)
2.4 Replacement Algorithm
16(1)
2.5 Cache Access Serial Versus Parallel
17(1)
2.6 Cache Architecture Design Example
17(12)
2.6.1 Data Arrays Banking Options
18(2)
2.6.2 Tag Array Design for High Associatively Cache
20(9)
3 Embedded Memory Hierarchy
29(8)
3.1 Memory Size, Access Time, and Power Relationships
29(1)
3.2 Memory Performance
30(1)
3.3 Memory Hierarchy for Multi-core General Purpose Processor and SOC
31(1)
3.4 Memory Hierarchy Overhead
32(1)
3.5 Cache Snooping
33(4)
4 SRAM-Based Memory Operation and Yield
37(16)
4.1 SRAM Cell and Array Design
37(7)
4.1.1 SRAM Cell Stability
38(3)
4.1.2 Write Completion
41(1)
4.1.3 SRAM Access Time
42(2)
4.2 Interaction Between Read and Write Operations
44(1)
4.3 Interaction Between Voltage, Power, and Performance
44(3)
4.4 Variation and Its Effect on Yield
47(2)
4.4.1 Fabrication-Related Variation
48(1)
4.4.2 Environment Variation
49(1)
4.4.3 Aging (Hot Electron, NBTI)
49(1)
4.5 Design with Variation
49(4)
5 Power and Yield for SRAM Memory
53(8)
5.1 Low Voltage and High Yield Approaches in SRAM Memory
53(1)
5.2 Process Technology Transistor Sizing and Layout
54(1)
5.3 Modified SRAM
55(1)
5.4 Voltage Islands and Separate Voltage Supplies
56(1)
5.5 Body Biase
57(1)
5.6 Read and Write Assist Circuits
57(4)
6 Leakage Reduction
61(8)
6.1 Usage of Head and Foot Switch for Leakage Reduction
62(2)
6.2 SRAM-Based Memory Leakage
64(1)
6.3 Design Example
65(2)
6.4 Proposed Low Leakage Wordline Logic
67(2)
7 Embedded Memory Verification
69(6)
7.1 ATPG View Generation for Memory
69(2)
7.2 Verification of ATPG Gate Level Model Versus Schematic
71(4)
7.2.1 DFT Compatibility Using ATPG Tool
71(2)
7.2.2 Validation Through HDL Simulation
73(1)
7.2.3 Validation with Golden Model
73(2)
8 Embedded Memory Design Validation and Design For Test
75(8)
8.1 Memory Organization and Operation Impact on DFT
76(1)
8.2 Testing and Memory Modeling
77(6)
8.2.1 Built in Self-Test
77(2)
8.2.2 Scan-Based Testing
79(1)
8.2.3 Function Testing
80(3)
9 Emerging Memory Technology Opportunities and Challenges
83(8)
9.1 Resistive Memory Principle
85(1)
9.2 Spin Torque Transfer Memory (STT-MRAM)
86(1)
9.3 Phase Change Memory
86(1)
9.4 Memristor
87(4)
References 91