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FPGA Prototyping By Verilog Examples: Xilinx Spartan3 Version [Kõva köide]

  • Formaat: Hardback, 518 pages, kõrgus x laius x paksus: 260x186x34 mm, kaal: 1080 g
  • Ilmumisaeg: 18-Jul-2008
  • Kirjastus: Wiley-Blackwell
  • ISBN-10: 0470185325
  • ISBN-13: 9780470185322
Teised raamatud teemal:
  • Formaat: Hardback, 518 pages, kõrgus x laius x paksus: 260x186x34 mm, kaal: 1080 g
  • Ilmumisaeg: 18-Jul-2008
  • Kirjastus: Wiley-Blackwell
  • ISBN-10: 0470185325
  • ISBN-13: 9780470185322
Teised raamatud teemal:
Hardware descriptive language (HDL) and field-programmable gate array (FPGA) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This text for a digital system design course introduces concepts and techniques of the HDL Verilog and FPGAs to designers through a series of hands-on experiments. The main focus of the book is on the effective derivation of hardware rather than the syntax of HDL. Instead of explaining every language construct, the book focus on a small synthesizable subset and uses about a dozen code templates to provide the skeletons of various types of circuits. Although the major goal of the book is to teach readers how to develop software-independent and device-neutral HDL codes, the book uses a software package and a prototyping board to synthesize and implement the design examples. The software used, a Web version of the Xilinx ISE package, is available free online. The book is intended to be used with several entry-level FPGA prototyping boards manufactured by Digilent, Inc. Readers should have a basic knowledge of digital systems and prior exposure to assembly language programming. Chu teaches in the Department of Electrical and Computer Engineering at Cleveland State University. Annotation ©2008 Book News, Inc., Portland, OR (booknews.com)

FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a “learn by doing” approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

Arvustused

Chu (Cleveland State University) has written several volumes covering Verilog and VHDL, the two major hardware definition languages used in the design of smaller digital systems. The volume reviewed here is an introduction to Verilog only. The book assumes that the student is already familiar with basic digital circuits. After an introductory section, the remainder of the work consists of worked examples that should be quite easily understood by students. Each chapter ends with suggested exercises that build directly on the examples from that chapter. There are sections that are specific to Xilinx Spartan FPGAs and in some cases, specific to the Digilent S3 prototyping board. A course that uses different hardware would need to provide supplementary material before using this book as a resource. Chu writes in a pedagogically sound manner and includes good coverage of the Verilog language, with nice attention to the differences between the 1995 and 2001 versions of the language. The volume suffers from some sloppy editing (e.g., a reference to VHDL instead of Verilog in one place, an incorrect timing parameter value in the appendix, miscellaneous typos) and a very skimpy index. Summing Up : Recommended. Upper-division undergraduate through professional collections. -- C. Vickery, Queens College of CUNY ( Choice, February 2009)

Preface xxi
Acknowledgments xxvii
PART I BASIC DIGITAL CIRCUITS
Gate-level combinational circuit
1(14)
Introduction
1(1)
General description
2(1)
Basic lexical elements and data types
3(1)
Lexical elements
3(1)
Data types
4(1)
Four-Value System
4(1)
Data type groups
4(1)
Number respresentation
5(1)
Operators
5(1)
Program skeleton
5(4)
Port declaration
6(1)
Program body
7(1)
Signal declaration
7(1)
Another example
8(1)
Structural description
9(3)
Testbench
12(2)
Bibliographic notes
14(1)
Suggested experiments
14(1)
Code for gate-lvel greater-than circuit
14(1)
Code for gate-level binary decorder
14(1)
Overview of FPGA and EDA software
15(24)
Introduction
15(1)
FPGA
15(2)
Overview of a general FPGA device
15(2)
Overview of the Xilinx Spartan-3 devices
17(1)
Overview of the Digilent S3 board
17(2)
Development flow
19(2)
Overview of the xilinx ISE project navigator
21(3)
Short tutorial on ISE project navigator
24(7)
Create the design project and HDL codes
25(1)
Create a testbench and perform the RTL simulation
26(1)
Add a constraint file and synthesize and implement the code
26(3)
Generate and download the configuration file to an FPGA device
29(2)
Short tutorial on the ModelSim HDL simualtor
31(4)
Bibliographic notes
35(1)
Suggested experiments
36(3)
Gate-lvel grater-than circuit
36(1)
Gate-level binary decoder
36(3)
RT-level combination circuit
39(44)
Introduciton
39(1)
Operators
39(9)
Arithmetic operatiors
41(1)
Shift operators
41(1)
Relational and equality operators
42(1)
Bitwise, reduction, and logical operators
42(1)
Concetenation and replication operators
43(1)
Conditional operators
44(1)
Operator precedence
44(1)
Expression bit-length adjustment
45(3)
Synthesis of z and x circuit
48(1)
Always block for a combinational circuit
48(3)
Basic syntax and behavior
48(1)
Procedural assignment
49(1)
Variable data types
49(1)
Simple examples
49(2)
If statement
51(3)
Syntax
51(1)
Example
52(2)
Case statement
54(3)
Syntax
54(1)
Example
54(2)
The casez and casex statements
56(1)
The full case and parallel case
56(1)
Routing structure of conditional control constructs
57(3)
Priority routing network
57(2)
Multiplexing network
59(1)
General coding guidelines for an always block
60(4)
Common errors in combinational circuit codes
60(3)
Guidelines
63(1)
Parameter and constant
64(3)
Constant
64(1)
Parameter
65(2)
Use of parameters in Verilog-1995
67(1)
Design examples
67(13)
Hexadecimal digit to seven-segment LED decoder
67(4)
Sign-magnitude adder
71(2)
Barrel shifter
73(2)
Simplified floating-point adders
75(5)
Bibliographic ntoes
80(1)
Suggested experiments
80(3)
Multifunction barrel shifter
80(1)
Dual-priority encoder
80(1)
BCD incrementor
81(1)
Floating-point greater-than circuit
81(1)
Floating-point grater-than circuit
81(1)
Floatin-point and signed integer conversin circuit
81(1)
Enhanced floating-point adder
81(2)
Regular Sequential Circuit
83(36)
Introduction
83(3)
D FF and register
83(1)
Synchronous system
84(1)
Code development
85(1)
HDL code of the FF and register
86(5)
D FF
86(3)
Register
89(1)
Register file
90(1)
Storage components in a Spartan-3 device
91(1)
Simple desing examples
91(5)
Shift register
91(2)
Binary counter and variant
93(3)
Testbench for sequential circuits
96(3)
Case study
99(16)
LED time-multiplexing circuit
99(8)
Stopwatch
107(3)
FIFO buffer
110(5)
Bibliographic notes
115(1)
Suggested experiments
115(4)
Programmable square-wave generator
115(1)
PWM and LED dimmer
115(1)
Rotating square circuit
116(1)
Heartbeat circuit
116(1)
Rotating LED banner circuit
116(1)
Enhanced stopwatch
116(1)
Stack
117(2)
FSM
119(20)
Introduction
119(3)
Mealy and Moore outputs
119(1)
FSM representation
120(2)
FSM code development
122(3)
Design examples
125(10)
Rising-edge detector
125(5)
Debouncing circuit
130(3)
Testing circuit
133(2)
Bibliographic notes
135(1)
Suggested experiments
135(4)
Dual-edge dectector
135(1)
Alternative debouncing circuit
135(1)
Parking lot occupancy counter
136(3)
FSMD
139(36)
Introduction
139(4)
Single RT operation
139(1)
ASMD chart
140(1)
Decision box with a register
141(2)
Code developemnt of an FSMD
143(10)
Debouncing circcuit based on RT methodology
144(2)
Code with explicit data path components
146(2)
Code with implicit data path components
148(2)
Comparison
150(2)
Testing circuit
152(1)
Design examples
153(17)
Fibonacci number circuit
153(4)
Division circuit
157(3)
Binary-to-BCD conversion circuit
160(4)
Period counter
164(3)
Accurate low-frequcney counter
167(3)
Bibliographic notes
170(1)
Suggested experiments
170(5)
Alternative debouncing circuit
170(1)
BCD-to-binary conversion circuit
171(1)
Fibonacci circuit with BCD I/O: design apprach 1
171(1)
Fibonacci circuit with BCD I/O: design approach 2
171(1)
Auto-scaled low-frequency counter
172(1)
Reactin timer
172(1)
Babbage differnce engine emulation circuit
173(2)
Selected Topics of Verilog
175(40)
Blocking versus nonblocking assignment
175(7)
Overview
175(2)
Combinational circuit
177(2)
Memory element
179(1)
Sequential circuit with mixed blocking and nonblocking assignments
180(2)
Alternative coding style for sequential circuit
182(6)
Binary counter
182(3)
FSM
185(1)
FSMD
186(2)
Summary
188(1)
Use of the signed data type
188(3)
Overview
188(1)
Signed nuber in Verilog-1995
189(1)
Signed number in Vriolog-2001
190(1)
Use of function in synthesis
191(2)
Overview
191(1)
Examples
192(1)
Additional constructs for testbench development
193(17)
Always block and initial blcok
194(1)
Procedural statements
194(2)
Timing control
196(1)
Delay control
196(1)
Event control
197(1)
Wait statement
197(1)
Timescale directive
197(1)
System functions and tasks
198(4)
User-defined functions and tasks
202(2)
Example of a comprehensive testbench
204(6)
Bibliographic notes
210(1)
Suggested experiments
210(5)
Shift register with blocking and nonblocking assignments
210
Alternative coding sytle for BCD counter
11(200)
Alternative coding sytle for FIFO buffer
211(1)
Alternative coding style for Fibonacci circuit
211(1)
Dual-mode comparator
211(1)
Enhanced binary counter monitor
212(1)
Testbench for FIFO buffer
212(3)
PART II I/O MODULES
Uart
215(20)
Introduction
215(1)
Uart receiving subsystem
216(4)
Oversampling procedure
216(1)
Baud rate generator
217(1)
Uart receiver
217(3)
Interface circuit
220(1)
Uart transmitting subsystema223
220(6)
Overall Uart System
226(4)
Complete Uart core
226(2)
Uart verification configuration
228(2)
Customizing a Uart
230(2)
Bibliogaphic notes
232(1)
Suggested experiments
232(3)
Full-featured Uart
232(1)
Uart with an automatic baud rate detection circuit
233(1)
Uart with an automatic baud rate and partiy detection circuit
233(1)
Uart-controlled stopwatch
233(1)
Uart-controlled rotating Led banner
234(1)
PS2 Keyboard
235(16)
Introduction
235(1)
PS2 receiving subsystem
236(4)
Physical interface of a PS2 port
236(1)
Device-to-host communication protocol
236(1)
Design and code
236(4)
PS2 keyboard scan code
240(4)
Overview of the scan code
240(1)
Scan code monitor circuit
241(3)
PS2 keyboard interface circuit
244(4)
Basic design and HDL code
244(2)
Verification circuit
246(2)
Bibliographic notes
248(1)
Suggested experiments
248(3)
Alternative keyboard interface I
248(1)
Alternative keyboard interface II
249(100)
PS2 receiving subsystem with watchdog timer
349
Keyboard-controlled stopwatch
249(1)
Keyboard-controlled rotating LED banner
249(2)
PS2 Mouse
251(18)
Introduction
251(1)
PS2 mouse protocol
252(1)
Basic operation
252(1)
Basic initialization procedure
252(1)
PS2 transmitting subsystem
253(6)
Host-to-PS2-device communication protocol
253(1)
Design and code
254(5)
Bidirectional PS2 interface
259(4)
Basic design and code
259(1)
Verification circuit
260(3)
PS2 mouse interface
263(3)
Basic design
263(2)
Testing circuit
265(1)
Bibliographic notes
266(1)
Suggested experiments
266(3)
Keyboard control circuit
267(1)
Enhanced mouse interface
267(1)
Mouse-controlled seven-segment LED display
267(2)
External SRAM
269(28)
Introduction
269(1)
Specification of the IS61LV25616AL Sram
270(4)
Block diagram and I/O signals
270(1)
Timing parameters
270(4)
Basic memory controller
274(2)
Block diagram
274(1)
Timing requirement
275(1)
Register file versus SRAM
276(1)
A safe design
276(12)
ASMD chart
276(1)
Timing analysis
277(1)
HDL implementation
278(3)
Basic testing circuit
281(2)
Comprehensive SRAM testing circuit
283(5)
More aggressive design
288(6)
Timing issues
288(1)
Alternative design I
288(2)
Alternative design II
290(1)
Aalternative design II
291(2)
Advanced FPGA features Dilini specific
293(1)
Bibliographic notes
294(1)
Suggested experiments
294(3)
Memory with a 512K-by-26 configuration
294(1)
Memory with a 1M-by-i configuration
295(1)
Memory with an 8M-by-1 configuration
295(1)
Expanded memory testing circuit
295(1)
Memory controller and testing circuit for altermative design I
295(1)
Memory controller and testng circuit for alternative design II
295(1)
Memory controller and testing circuit for alternative design III
295(1)
Memory controller with DCM
295(1)
High-performance memory controller
296(1)
Xilinx Sartan-3 Specific Memory
297(12)
Introduction
297(1)
Embedded memory of Spartan-3 device
297(1)
Overview
297(1)
Comparison
298(1)
Method to incorporate memory modules
298(2)
Memory module via HDL component instantiation
299(1)
Memory module via Core Generator
299(1)
Memory module via HDL infrerence
300(1)
HDL templates for memory inference
300(7)
Single-port RAM
300(3)
Dual-port RAM
303(2)
ROM
305(2)
Bibliographic notes
307(1)
Suggested expriments
307(2)
Block-RAM-based FIFO
307(1)
Block-RAM-based stack
307(1)
ROM-based sign-magnitude adder
307(1)
ROM-based sin (I) function
308(1)
ROM-based sin (x) and cos(x) functions
308(1)
VGA controller I: graphic
309(32)
Introduction
309(3)
Basic operation of a CRT
309(2)
VGA port of the S3 board
311(1)
Video controller
311(1)
VGA synchronization
312(7)
Horizontal synchronization
312(2)
Vertical synchronization
314(1)
Timing calculation of VGA synchronization signals
315(1)
HDL implementation
315(3)
Testing circuit
318(1)
Overview of the pixel generation circuit
319(1)
Graphic generation with an object-mapped scheme
319(13)
Rectangular objects
320(5)
Non-rectangular object
325(1)
Animated object
326(6)
Graphic generation with a bit-mapped scheme
332(5)
Dual-port RAM implementation
332(5)
Single-port RAM implementation
337(1)
Bibliographic notes
337(1)
Suggested expriments
337(4)
VGA test pattern generator
337(1)
SVGA mode synchronization circuit
338(1)
Visible screen adjustmetn circuit
338(1)
Ball-in-a-box circuit
338(1)
Two-ball-in-a-box circuit
339(1)
Two-player pong game
339(1)
Breakout game
339(1)
Full-screen dot trace
339(1)
Mouse pointercircuit
340(1)
Small-screen mouse scribble circuit
340(1)
Full-screen mouse scribble circuit
340(1)
VGA controller II: text
341(30)
Introduction
341(1)
Text generation
341(7)
Character as a tile
341(1)
Font ROM
342(2)
Basic text generation circuit
344(1)
Font display circuit
345(2)
Font scaling
347(1)
Full-screen text display
348(4)
The complete pong game
352(14)
Text subsystem
352(6)
Modified graphic subsystem
358(1)
Auxiliary conuters
359(2)
Top-level system
361(5)
Bibliographic notes
366(1)
Suggested experiments
366(5)
Rotating banner
366(1)
Underline for the cursor
366(1)
Dual-mode text display
366(1)
Keyboard text entry
366(1)
Uart terminal
366(1)
Square-wave display
367(1)
Simple for-trace logic analyzer
367(1)
Complete two-player pong game
368(1)
Complete breakout game
368(3)
PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC
PicoBlaze Overivew
371(22)
Introduction
371(1)
Customized hardware and customized software
372(2)
From special-purpose FSMD to general-purpose microcontroller
372(2)
Application of microcontroller
374(1)
Overview of PicoBlaze
374(3)
Basic organization
374(2)
Top-level HDL modules
376(1)
Development flow
377(1)
Instructionset
377(13)
Programming model
379(1)
Instrcution format
379(1)
Logical instructions
380(1)
Artihmetic instructions
381(1)
Compare and test instructions
382(1)
Shift and rotate instructions
383(1)
Data movement instructions
384(2)
Program flow control instructions
386(3)
Interrupt related instructions
389(1)
Assembler directive
390(1)
The KCPM3 directives
390(1)
The PBlazeIDE directives
390(1)
Bibliographic notes
391(2)
PicoBlaze Assembly Code Development
393(22)
Introduction
393(1)
Useful code segments
393(5)
KCPSM3 conventions
393(1)
Bit manifpulation
394(1)
Multiple-byte manipulation
395(1)
Control structure
396(2)
Subroutin development
398(1)
Program development
399(7)
Demonstration example
400(4)
Program documentation
404(2)
Processing of the assembly code
406(5)
Compiling with KCSPM3
406(1)
Simulation by PBlazeIDE
407(3)
Reloading code via the JTAG port
410(1)
Compiing by PBlazeIDE
410(1)
Syntheses with PicoBlaze
411(1)
Bibliographic notes
412(1)
Suggested experiments
412(3)
Signed multiplication
412(1)
Multi-bute multiplication
412(1)
Barrel shift function
413(1)
Reverse function
413(1)
Binary-to-BCD conversion
413(1)
BCD-to-binary conversion
413(1)
Heartbeat circuit
413(1)
Rotating LED circuit
413(1)
Discrete LED dimmer
413(2)
PicoBlaze I/O Interface
415(38)
Introduction
415(1)
Output port
416(2)
Output instruction and timing
416(1)
Output interface
417(1)
Input port
418(3)
Input instruction and timing
418(1)
Input interface
419(2)
Square program with a switch and seven-segment LED display interface
421(13)
Output interface
421(1)
Input interface
422(2)
Assemble code development
424(7)
HDL code development
431(3)
Square program with a combnational multipler and Uart console
434(15)
Multiplier interface
434(1)
Uart interface
435(1)
Assembly code development
436(10)
HDL code development
446(3)
Bibliographic notes
449(1)
Suggested experiments
449(4)
Low-frequency counter I
449(1)
Low-frequency counter
449(1)
Auto-scaled low-frequency counter
449(1)
Basic reaction timer with a software timer
449(1)
Basic reaction timer with a hardware timer
450(1)
Enhanced reation timer
450(1)
Small-screen mouse scribble circuit
450(1)
Full-screen mouse scribble circuit
450(1)
Enhanced rotating banner
450(1)
Pong game
450(1)
Text editor
451(2)
PicoBlaze Interrupt Interface
453(14)
Intrdocution
453(1)
Interrupt handling in PicoBlaze
453(3)
Software processing
454(1)
Timing
455(1)
External interface
456(1)
Single interrupt request
456(1)
Multiple interrupt requests
456(1)
Software development considerations
457(1)
Interrupt as an alternative scheduling scheme
457(1)
Developmetn of an interrupt service routine
458(1)
Design example
458(6)
Interupt interface
458(1)
Interrupt service routine development
459(1)
Assembly code development
459(2)
HDL code development
461(3)
Bibliographic notes
464(1)
Suggested experiments
464(3)
Alternative timer interrupt service routine
464(1)
Programmable timer
464(1)
Set-button interrupt service routine
465(1)
Interrupt interface with two requests
465(1)
Four-request interrupt controller
465(2)
Apendix A: Sample Verilog templates
467(18)
Numbers and operators
467(2)
Sized and unsized numbrs
467(1)
Operators
468(1)
General Verilog constructs
469(1)
Overall code structure
469(1)
Component instantiation
470(1)
Routing with conditional operator and if and case statements
470(2)
Conditional operator and if statement
470(1)
Case statement
471(1)
Combinational circuit using an always block
472(1)
Always block without default output assignment
472(1)
Always block with default output assignment
472(1)
Memory Components
473(1)
Register template
473(1)
Register file
474(1)
Regular sequential circuits
474(2)
FSM
476(2)
FSMD
478(2)
S3 board constraint file (s3.ucf)
480(5)
References 485(2)
Topic Index 487
Pong P. Chu, PhD, is Associate Professor in the Department of Electrical and Computer Engineering at Cleveland State University in Ohio. He has taught undergraduate and graduatelevel digital systems and computer architecture courses for more than a decade and has received instructional grants from the National Science Foundation and Cleveland State University.