Preface |
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xxi | |
Acknowledgments |
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xxvii | |
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PART I BASIC DIGITAL CIRCUITS |
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Gate-level combinational circuit |
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1 | (14) |
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1 | (1) |
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2 | (1) |
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Basic lexical elements and data types |
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3 | (1) |
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3 | (1) |
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4 | (1) |
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4 | (1) |
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4 | (1) |
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5 | (1) |
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5 | (1) |
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5 | (4) |
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6 | (1) |
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7 | (1) |
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7 | (1) |
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8 | (1) |
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9 | (3) |
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12 | (2) |
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14 | (1) |
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14 | (1) |
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Code for gate-lvel greater-than circuit |
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14 | (1) |
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Code for gate-level binary decorder |
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14 | (1) |
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Overview of FPGA and EDA software |
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15 | (24) |
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15 | (1) |
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15 | (2) |
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Overview of a general FPGA device |
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15 | (2) |
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Overview of the Xilinx Spartan-3 devices |
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17 | (1) |
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Overview of the Digilent S3 board |
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17 | (2) |
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19 | (2) |
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Overview of the xilinx ISE project navigator |
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21 | (3) |
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Short tutorial on ISE project navigator |
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24 | (7) |
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Create the design project and HDL codes |
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25 | (1) |
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Create a testbench and perform the RTL simulation |
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26 | (1) |
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Add a constraint file and synthesize and implement the code |
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26 | (3) |
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Generate and download the configuration file to an FPGA device |
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29 | (2) |
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Short tutorial on the ModelSim HDL simualtor |
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31 | (4) |
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35 | (1) |
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36 | (3) |
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Gate-lvel grater-than circuit |
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36 | (1) |
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Gate-level binary decoder |
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36 | (3) |
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RT-level combination circuit |
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39 | (44) |
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39 | (1) |
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39 | (9) |
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41 | (1) |
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41 | (1) |
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Relational and equality operators |
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42 | (1) |
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Bitwise, reduction, and logical operators |
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42 | (1) |
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Concetenation and replication operators |
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43 | (1) |
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44 | (1) |
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44 | (1) |
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Expression bit-length adjustment |
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45 | (3) |
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Synthesis of z and x circuit |
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48 | (1) |
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Always block for a combinational circuit |
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48 | (3) |
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Basic syntax and behavior |
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48 | (1) |
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49 | (1) |
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49 | (1) |
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49 | (2) |
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51 | (3) |
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51 | (1) |
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52 | (2) |
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54 | (3) |
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54 | (1) |
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54 | (2) |
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The casez and casex statements |
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56 | (1) |
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The full case and parallel case |
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56 | (1) |
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Routing structure of conditional control constructs |
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57 | (3) |
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57 | (2) |
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59 | (1) |
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General coding guidelines for an always block |
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60 | (4) |
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Common errors in combinational circuit codes |
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60 | (3) |
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63 | (1) |
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64 | (3) |
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64 | (1) |
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65 | (2) |
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Use of parameters in Verilog-1995 |
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67 | (1) |
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67 | (13) |
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Hexadecimal digit to seven-segment LED decoder |
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67 | (4) |
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71 | (2) |
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73 | (2) |
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Simplified floating-point adders |
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75 | (5) |
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80 | (1) |
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80 | (3) |
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Multifunction barrel shifter |
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80 | (1) |
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80 | (1) |
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81 | (1) |
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Floating-point greater-than circuit |
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81 | (1) |
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Floating-point grater-than circuit |
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81 | (1) |
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Floatin-point and signed integer conversin circuit |
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81 | (1) |
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Enhanced floating-point adder |
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81 | (2) |
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Regular Sequential Circuit |
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83 | (36) |
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83 | (3) |
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83 | (1) |
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84 | (1) |
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85 | (1) |
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HDL code of the FF and register |
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86 | (5) |
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86 | (3) |
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89 | (1) |
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90 | (1) |
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Storage components in a Spartan-3 device |
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91 | (1) |
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91 | (5) |
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91 | (2) |
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Binary counter and variant |
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93 | (3) |
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Testbench for sequential circuits |
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96 | (3) |
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99 | (16) |
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LED time-multiplexing circuit |
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99 | (8) |
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107 | (3) |
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110 | (5) |
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115 | (1) |
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115 | (4) |
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Programmable square-wave generator |
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115 | (1) |
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115 | (1) |
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116 | (1) |
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116 | (1) |
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Rotating LED banner circuit |
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116 | (1) |
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116 | (1) |
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117 | (2) |
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119 | (20) |
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119 | (3) |
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119 | (1) |
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120 | (2) |
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122 | (3) |
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125 | (10) |
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125 | (5) |
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130 | (3) |
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133 | (2) |
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135 | (1) |
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135 | (4) |
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135 | (1) |
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Alternative debouncing circuit |
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135 | (1) |
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Parking lot occupancy counter |
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136 | (3) |
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139 | (36) |
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139 | (4) |
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139 | (1) |
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140 | (1) |
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Decision box with a register |
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141 | (2) |
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Code developemnt of an FSMD |
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143 | (10) |
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Debouncing circcuit based on RT methodology |
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144 | (2) |
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Code with explicit data path components |
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146 | (2) |
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Code with implicit data path components |
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148 | (2) |
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150 | (2) |
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152 | (1) |
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153 | (17) |
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153 | (4) |
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157 | (3) |
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Binary-to-BCD conversion circuit |
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160 | (4) |
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164 | (3) |
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Accurate low-frequcney counter |
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167 | (3) |
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170 | (1) |
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170 | (5) |
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Alternative debouncing circuit |
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170 | (1) |
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BCD-to-binary conversion circuit |
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171 | (1) |
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Fibonacci circuit with BCD I/O: design apprach 1 |
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171 | (1) |
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Fibonacci circuit with BCD I/O: design approach 2 |
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171 | (1) |
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Auto-scaled low-frequency counter |
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172 | (1) |
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172 | (1) |
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Babbage differnce engine emulation circuit |
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173 | (2) |
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Selected Topics of Verilog |
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175 | (40) |
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Blocking versus nonblocking assignment |
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175 | (7) |
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175 | (2) |
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177 | (2) |
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179 | (1) |
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Sequential circuit with mixed blocking and nonblocking assignments |
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180 | (2) |
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Alternative coding style for sequential circuit |
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182 | (6) |
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182 | (3) |
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185 | (1) |
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186 | (2) |
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188 | (1) |
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Use of the signed data type |
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188 | (3) |
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188 | (1) |
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Signed nuber in Verilog-1995 |
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189 | (1) |
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Signed number in Vriolog-2001 |
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190 | (1) |
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Use of function in synthesis |
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191 | (2) |
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191 | (1) |
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192 | (1) |
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Additional constructs for testbench development |
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193 | (17) |
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Always block and initial blcok |
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194 | (1) |
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194 | (2) |
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196 | (1) |
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196 | (1) |
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197 | (1) |
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197 | (1) |
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197 | (1) |
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System functions and tasks |
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198 | (4) |
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User-defined functions and tasks |
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202 | (2) |
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Example of a comprehensive testbench |
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204 | (6) |
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210 | (1) |
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210 | (5) |
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Shift register with blocking and nonblocking assignments |
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210 | |
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Alternative coding sytle for BCD counter |
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11 | (200) |
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Alternative coding sytle for FIFO buffer |
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211 | (1) |
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Alternative coding style for Fibonacci circuit |
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211 | (1) |
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211 | (1) |
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Enhanced binary counter monitor |
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212 | (1) |
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Testbench for FIFO buffer |
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212 | (3) |
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215 | (20) |
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215 | (1) |
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216 | (4) |
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216 | (1) |
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217 | (1) |
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217 | (3) |
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220 | (1) |
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Uart transmitting subsystema223 |
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220 | (6) |
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226 | (4) |
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226 | (2) |
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Uart verification configuration |
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228 | (2) |
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230 | (2) |
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232 | (1) |
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232 | (3) |
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232 | (1) |
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Uart with an automatic baud rate detection circuit |
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233 | (1) |
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Uart with an automatic baud rate and partiy detection circuit |
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233 | (1) |
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Uart-controlled stopwatch |
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233 | (1) |
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Uart-controlled rotating Led banner |
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234 | (1) |
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235 | (16) |
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235 | (1) |
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236 | (4) |
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Physical interface of a PS2 port |
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236 | (1) |
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Device-to-host communication protocol |
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236 | (1) |
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236 | (4) |
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240 | (4) |
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Overview of the scan code |
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240 | (1) |
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Scan code monitor circuit |
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241 | (3) |
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PS2 keyboard interface circuit |
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244 | (4) |
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Basic design and HDL code |
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244 | (2) |
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246 | (2) |
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248 | (1) |
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248 | (3) |
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Alternative keyboard interface I |
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248 | (1) |
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Alternative keyboard interface II |
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249 | (100) |
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PS2 receiving subsystem with watchdog timer |
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349 | |
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Keyboard-controlled stopwatch |
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249 | (1) |
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Keyboard-controlled rotating LED banner |
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249 | (2) |
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251 | (18) |
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251 | (1) |
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252 | (1) |
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252 | (1) |
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Basic initialization procedure |
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252 | (1) |
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PS2 transmitting subsystem |
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253 | (6) |
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Host-to-PS2-device communication protocol |
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253 | (1) |
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254 | (5) |
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Bidirectional PS2 interface |
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259 | (4) |
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259 | (1) |
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260 | (3) |
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263 | (3) |
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263 | (2) |
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265 | (1) |
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266 | (1) |
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266 | (3) |
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267 | (1) |
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267 | (1) |
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Mouse-controlled seven-segment LED display |
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267 | (2) |
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269 | (28) |
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269 | (1) |
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Specification of the IS61LV25616AL Sram |
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270 | (4) |
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Block diagram and I/O signals |
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270 | (1) |
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270 | (4) |
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274 | (2) |
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274 | (1) |
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275 | (1) |
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Register file versus SRAM |
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276 | (1) |
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276 | (12) |
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276 | (1) |
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277 | (1) |
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278 | (3) |
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281 | (2) |
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Comprehensive SRAM testing circuit |
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283 | (5) |
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288 | (6) |
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288 | (1) |
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288 | (2) |
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290 | (1) |
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291 | (2) |
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Advanced FPGA features Dilini specific |
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293 | (1) |
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294 | (1) |
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294 | (3) |
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Memory with a 512K-by-26 configuration |
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294 | (1) |
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Memory with a 1M-by-i configuration |
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295 | (1) |
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Memory with an 8M-by-1 configuration |
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295 | (1) |
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Expanded memory testing circuit |
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295 | (1) |
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Memory controller and testing circuit for altermative design I |
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295 | (1) |
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Memory controller and testng circuit for alternative design II |
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295 | (1) |
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Memory controller and testing circuit for alternative design III |
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295 | (1) |
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Memory controller with DCM |
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295 | (1) |
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High-performance memory controller |
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296 | (1) |
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Xilinx Sartan-3 Specific Memory |
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297 | (12) |
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297 | (1) |
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Embedded memory of Spartan-3 device |
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297 | (1) |
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297 | (1) |
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298 | (1) |
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Method to incorporate memory modules |
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298 | (2) |
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Memory module via HDL component instantiation |
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299 | (1) |
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Memory module via Core Generator |
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299 | (1) |
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Memory module via HDL infrerence |
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300 | (1) |
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HDL templates for memory inference |
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300 | (7) |
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300 | (3) |
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303 | (2) |
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305 | (2) |
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307 | (1) |
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307 | (2) |
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307 | (1) |
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307 | (1) |
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ROM-based sign-magnitude adder |
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307 | (1) |
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ROM-based sin (I) function |
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308 | (1) |
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ROM-based sin (x) and cos(x) functions |
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308 | (1) |
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VGA controller I: graphic |
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309 | (32) |
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309 | (3) |
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309 | (2) |
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311 | (1) |
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311 | (1) |
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312 | (7) |
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Horizontal synchronization |
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312 | (2) |
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314 | (1) |
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Timing calculation of VGA synchronization signals |
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315 | (1) |
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315 | (3) |
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318 | (1) |
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Overview of the pixel generation circuit |
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319 | (1) |
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Graphic generation with an object-mapped scheme |
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319 | (13) |
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320 | (5) |
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325 | (1) |
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326 | (6) |
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Graphic generation with a bit-mapped scheme |
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332 | (5) |
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Dual-port RAM implementation |
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332 | (5) |
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Single-port RAM implementation |
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337 | (1) |
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337 | (1) |
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337 | (4) |
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VGA test pattern generator |
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337 | (1) |
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SVGA mode synchronization circuit |
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338 | (1) |
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Visible screen adjustmetn circuit |
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338 | (1) |
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338 | (1) |
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Two-ball-in-a-box circuit |
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339 | (1) |
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339 | (1) |
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339 | (1) |
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339 | (1) |
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340 | (1) |
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Small-screen mouse scribble circuit |
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340 | (1) |
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Full-screen mouse scribble circuit |
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340 | (1) |
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341 | (30) |
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341 | (1) |
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341 | (7) |
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341 | (1) |
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342 | (2) |
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Basic text generation circuit |
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344 | (1) |
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345 | (2) |
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347 | (1) |
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348 | (4) |
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352 | (14) |
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352 | (6) |
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Modified graphic subsystem |
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358 | (1) |
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359 | (2) |
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361 | (5) |
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366 | (1) |
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366 | (5) |
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366 | (1) |
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366 | (1) |
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366 | (1) |
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366 | (1) |
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366 | (1) |
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367 | (1) |
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Simple for-trace logic analyzer |
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367 | (1) |
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Complete two-player pong game |
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368 | (1) |
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368 | (3) |
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PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC |
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371 | (22) |
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371 | (1) |
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Customized hardware and customized software |
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372 | (2) |
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From special-purpose FSMD to general-purpose microcontroller |
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372 | (2) |
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Application of microcontroller |
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374 | (1) |
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374 | (3) |
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374 | (2) |
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376 | (1) |
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377 | (1) |
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377 | (13) |
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379 | (1) |
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379 | (1) |
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380 | (1) |
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381 | (1) |
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Compare and test instructions |
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382 | (1) |
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Shift and rotate instructions |
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383 | (1) |
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Data movement instructions |
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384 | (2) |
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Program flow control instructions |
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386 | (3) |
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Interrupt related instructions |
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389 | (1) |
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390 | (1) |
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390 | (1) |
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390 | (1) |
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391 | (2) |
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PicoBlaze Assembly Code Development |
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393 | (22) |
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393 | (1) |
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393 | (5) |
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393 | (1) |
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394 | (1) |
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Multiple-byte manipulation |
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395 | (1) |
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396 | (2) |
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398 | (1) |
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399 | (7) |
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400 | (4) |
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404 | (2) |
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Processing of the assembly code |
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406 | (5) |
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406 | (1) |
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407 | (3) |
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Reloading code via the JTAG port |
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410 | (1) |
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410 | (1) |
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411 | (1) |
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412 | (1) |
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412 | (3) |
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412 | (1) |
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Multi-bute multiplication |
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412 | (1) |
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413 | (1) |
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413 | (1) |
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413 | (1) |
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413 | (1) |
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413 | (1) |
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413 | (1) |
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413 | (2) |
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415 | (38) |
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415 | (1) |
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416 | (2) |
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Output instruction and timing |
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416 | (1) |
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417 | (1) |
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418 | (3) |
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Input instruction and timing |
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418 | (1) |
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419 | (2) |
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Square program with a switch and seven-segment LED display interface |
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|
421 | (13) |
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421 | (1) |
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422 | (2) |
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Assemble code development |
|
|
424 | (7) |
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|
431 | (3) |
|
Square program with a combnational multipler and Uart console |
|
|
434 | (15) |
|
|
434 | (1) |
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|
435 | (1) |
|
Assembly code development |
|
|
436 | (10) |
|
|
446 | (3) |
|
|
449 | (1) |
|
|
449 | (4) |
|
|
449 | (1) |
|
|
449 | (1) |
|
Auto-scaled low-frequency counter |
|
|
449 | (1) |
|
Basic reaction timer with a software timer |
|
|
449 | (1) |
|
Basic reaction timer with a hardware timer |
|
|
450 | (1) |
|
|
450 | (1) |
|
Small-screen mouse scribble circuit |
|
|
450 | (1) |
|
Full-screen mouse scribble circuit |
|
|
450 | (1) |
|
|
450 | (1) |
|
|
450 | (1) |
|
|
451 | (2) |
|
PicoBlaze Interrupt Interface |
|
|
453 | (14) |
|
|
453 | (1) |
|
Interrupt handling in PicoBlaze |
|
|
453 | (3) |
|
|
454 | (1) |
|
|
455 | (1) |
|
|
456 | (1) |
|
|
456 | (1) |
|
Multiple interrupt requests |
|
|
456 | (1) |
|
Software development considerations |
|
|
457 | (1) |
|
Interrupt as an alternative scheduling scheme |
|
|
457 | (1) |
|
Developmetn of an interrupt service routine |
|
|
458 | (1) |
|
|
458 | (6) |
|
|
458 | (1) |
|
Interrupt service routine development |
|
|
459 | (1) |
|
Assembly code development |
|
|
459 | (2) |
|
|
461 | (3) |
|
|
464 | (1) |
|
|
464 | (3) |
|
Alternative timer interrupt service routine |
|
|
464 | (1) |
|
|
464 | (1) |
|
Set-button interrupt service routine |
|
|
465 | (1) |
|
Interrupt interface with two requests |
|
|
465 | (1) |
|
Four-request interrupt controller |
|
|
465 | (2) |
|
Apendix A: Sample Verilog templates |
|
|
467 | (18) |
|
|
467 | (2) |
|
|
467 | (1) |
|
|
468 | (1) |
|
General Verilog constructs |
|
|
469 | (1) |
|
|
469 | (1) |
|
|
470 | (1) |
|
Routing with conditional operator and if and case statements |
|
|
470 | (2) |
|
Conditional operator and if statement |
|
|
470 | (1) |
|
|
471 | (1) |
|
Combinational circuit using an always block |
|
|
472 | (1) |
|
Always block without default output assignment |
|
|
472 | (1) |
|
Always block with default output assignment |
|
|
472 | (1) |
|
|
473 | (1) |
|
|
473 | (1) |
|
|
474 | (1) |
|
Regular sequential circuits |
|
|
474 | (2) |
|
|
476 | (2) |
|
|
478 | (2) |
|
S3 board constraint file (s3.ucf) |
|
|
480 | (5) |
References |
|
485 | (2) |
Topic Index |
|
487 | |