Pereface to the first edition |
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xi | |
Preface to the second edition |
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xiii | |
Physical constants and unit conversions |
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xv | |
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xvi | |
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1 | (10) |
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Evolution of VLSI Device Technology |
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1 | (3) |
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1 | (3) |
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4 | (1) |
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4 | (2) |
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4 | (1) |
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Modern Bipolar Transistors |
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5 | (1) |
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Scope and Brief Description of the Book |
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6 | (5) |
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11 | (137) |
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Electrons and Holes in Silicon |
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11 | (24) |
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11 | (6) |
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n-Type and p-Type Silicon |
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17 | (6) |
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Carrier Transport in Silicon |
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23 | (4) |
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Basic Equations for Device Operation |
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27 | (8) |
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35 | (37) |
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Energy-Band Diagrams for a p-n Diode |
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35 | (3) |
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38 | (8) |
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46 | (5) |
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Current-Voltage Characteristics |
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51 | (13) |
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Time-Dependent and Switching Characteristics |
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64 | (6) |
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70 | (2) |
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72 | (36) |
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Surface Potential: Accumulation, Depletion, and Inversion |
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72 | (6) |
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Electrostatic Potential and Charge Distribution in Silicon |
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78 | (7) |
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Capacitances in an MOS Structure |
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85 | (6) |
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Polysilicon-Gate Work Function and Depletion Effects |
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91 | (3) |
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MOS under Nonequilibrium and Gated Diodes |
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94 | (4) |
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Charge in Silicon Dioxide and at the Silicon-Oxide Interface |
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98 | (5) |
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Effect of Interface Traps and Oxide Charge on Device Characteristics |
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103 | (5) |
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108 | (14) |
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Static Characteristics of a Schottky Barrier Diode |
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108 | (7) |
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Current Transport in a Schottky Barrier Diode |
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115 | (1) |
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Current-Voltage Characteristics of a Schottky Barrier Diode |
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115 | (5) |
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120 | (2) |
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122 | (26) |
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Impact lonization and Avalanche Breakdown |
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122 | (3) |
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125 | (2) |
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Tunneling into and through Silicon Dioxide |
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127 | (6) |
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Injection of Hot Carriers from Silicon into Silicon Dioxide |
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133 | (2) |
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High-Field Effects in Gated Diodes |
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135 | (2) |
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137 | (4) |
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141 | (7) |
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148 | (56) |
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148 | (27) |
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149 | (6) |
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MOSFET I-V Characteristics |
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155 | (8) |
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Subthreshold Characteristics |
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163 | (3) |
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Substrate Bias and Temperature Dependence of Threshold Voltage |
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166 | (3) |
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169 | (3) |
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MOSFET Capacitances and Inversion-Layer Capacitance Effect |
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172 | (3) |
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175 | (29) |
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176 | (10) |
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Velocity Saturation and High-Field Transport |
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186 | (9) |
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Channel Length Modulation |
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195 | (1) |
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Source-Drain Series Resistance |
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196 | (1) |
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MOSFET Degradation and Breakdown at High Fields |
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196 | (5) |
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201 | (3) |
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204 | (52) |
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204 | (8) |
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204 | (3) |
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207 | (3) |
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210 | (2) |
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212 | (30) |
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Threshold Voltage Requirement |
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213 | (4) |
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217 | (7) |
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224 | (10) |
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Quantum Effect on Threshold Voltage |
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234 | (5) |
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Discrete Dopant Effects on Threshold Voltage |
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239 | (3) |
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242 | (14) |
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Various Definitions of Channel Length |
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242 | (2) |
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Extraction of the Effective Channel Length |
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244 | (4) |
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Physical Meaning of Effective Channel Length |
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248 | (4) |
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Extraction of Channel Length by C---V Measurements |
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252 | (2) |
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254 | (2) |
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256 | (62) |
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Basic CMOS Circuit Elements |
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256 | (17) |
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256 | (10) |
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266 | (4) |
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Inverter and NAND Layouts |
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270 | (3) |
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273 | (16) |
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274 | (3) |
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277 | (3) |
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280 | (3) |
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283 | (6) |
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Sensitivity of CMOS Delay to Device Parameters |
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289 | (18) |
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Propagation Delay and Delay Equation |
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289 | (7) |
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Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness |
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296 | (3) |
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Sensitivity of Delay to Power-Supply Voltage and Threshold Voltage |
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299 | (2) |
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Sensitivity of Delay to Parasitic Resistance and Capacitance |
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301 | (3) |
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Delay of Two-Way NAND and Body Effect |
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304 | (3) |
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Performance Factors of Advanced CMOS Devices |
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307 | (11) |
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308 | (3) |
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Effect of Transport Parameters on CMOS Performance |
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311 | (1) |
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312 | (3) |
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315 | (3) |
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318 | (56) |
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318 | (9) |
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Basic Operation of a Bipolar Transistor |
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322 | (1) |
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Modifying the Simple Diode Theory for Describing Bipolar Transistors |
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322 | (5) |
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Ideal Current-Voltage Characteristics |
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327 | (10) |
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329 | (1) |
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330 | (4) |
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334 | (2) |
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Ideal IC-VCE Characteristics |
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336 | (1) |
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Characteristics of a Typical n-p-n Transistor |
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337 | (15) |
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Effect of Emitter and Base Series Resistances |
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338 | (2) |
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Effect of Base-Collector Voltage on Collector Current |
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340 | (3) |
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Collector Current Falloff at High Currents |
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343 | (4) |
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Nonideal Base Current at Low Currents |
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347 | (5) |
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Bipolar Device Models for Circuit and Time-Dependent Analyses |
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352 | (14) |
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352 | (3) |
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355 | (1) |
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Small-Signal Equivalent-Circuit Model |
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356 | (3) |
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Emitter Diffusion Capacitance |
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359 | (2) |
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361 | (5) |
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366 | (8) |
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Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche |
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367 | (2) |
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Saturation Currents in a Transistor |
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369 | (1) |
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Relation Between BVCEO and BVcbo |
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370 | (1) |
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371 | (3) |
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374 | (63) |
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Design of the Emitter Region |
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374 | (3) |
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Diffused or Implanted-and-Diffused Emitter |
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375 | (1) |
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376 | (1) |
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Design of the Base Region |
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377 | (8) |
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Relationship between Base Sheet Resistivity and Collector Current Density |
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378 | (2) |
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Intrinsic-Base Dopant Distribution |
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380 | (1) |
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Electric Field in the Quasineutral Intrinsic Base |
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381 | (3) |
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384 | (1) |
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Design of the Collector Region |
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385 | (4) |
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Collector Design When There Is Negligible Base Widening |
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387 | (1) |
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Collector Design When There Is Appreciable Base Widening |
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388 | (1) |
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SiGe-Base Bipolar Transistors |
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389 | (40) |
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Transistors Having a Simple Linearly Graded Base Bandgap |
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390 | (6) |
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Base Current When Ge Is Present in the Emitter |
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396 | (5) |
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Transistors Having a Trapezoidal Ge Distribution in the Base |
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401 | (5) |
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Transistors Having a Constant Ge Distribution in the Base |
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406 | (4) |
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Effect of Emitter Depth Variation on Device Characteristics |
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410 | (4) |
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414 | (5) |
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Base-Width Modulation by VBE |
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419 | (4) |
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Reverse-Mode I-V Characteristics |
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423 | (3) |
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Heterojunction Nature of a SiGe-Base Bipolar Transistor |
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426 | (3) |
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Modern Bipolar Transistor Structures |
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429 | (8) |
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429 | (1) |
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430 | (1) |
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Self-Aligned Polysilicon Base Contact |
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430 | (1) |
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431 | (1) |
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431 | (1) |
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432 | (5) |
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Bipolar Performance Factors |
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437 | (39) |
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Figures of Merit of a Bipolar Transistor |
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437 | (4) |
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437 | (3) |
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Maximum Oscillation Frequency |
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440 | (1) |
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Ring Oscillator and Gate Delay |
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440 | (1) |
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441 | (6) |
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Delay Components of a Logic Gate |
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442 | (3) |
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Device Structure and Layout for Digital Circuits |
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445 | (2) |
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Bipolar Device Optimization for Digital Circuits |
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447 | (10) |
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Design Points for a Digital Circuit |
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447 | (1) |
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Device Optimization When There Is Significant Base Widening |
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448 | (1) |
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Device Optimization When There Is Negligible Base Widening |
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449 | (4) |
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Device Optimization for Small Power-Delay Product |
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453 | (2) |
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Bipolar Device Optimization from Some Data Analyses |
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455 | (2) |
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Bipolar Device Scaling for ECL Circuits |
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457 | (6) |
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458 | (2) |
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Limits in Bipolar Device Scaling for ECL Circuits |
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460 | (3) |
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Bipolar Device Optimization and Scaling for RF and Analog Circuits |
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463 | (6) |
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The Single-Transistor Amplifier |
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463 | (1) |
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Optimizing the Individual Parameters |
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464 | (3) |
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Technology for RF and Analog Bipolar Devices |
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467 | (1) |
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Limits in Scaling Bipolar Transistors for RF and Analog Applications |
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468 | (1) |
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Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT |
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469 | (7) |
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472 | (4) |
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476 | (41) |
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Static Random-Access Memory |
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477 | (18) |
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478 | (8) |
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Other Bistable MOSFET SRAM Cells |
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486 | (1) |
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487 | (8) |
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Dynamic Random-Access Memory |
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495 | (5) |
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Basic DRAM Cell and Its Operation |
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496 | (3) |
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Device Design and Scaling Considerations for a DRAM Cell |
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499 | (1) |
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500 | (17) |
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MOSFET Nonvolatile Memory Devices |
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501 | (6) |
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507 | (4) |
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Floating-Gate Nonvolatile Memory Cells |
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511 | (3) |
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Nonvolatile Memory Cells with Charge Stored in Insulator |
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514 | (2) |
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516 | (1) |
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Silicon-on-Insulator Devices |
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517 | (21) |
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517 | (6) |
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Partially Depleted SOI MOSFETs |
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518 | (2) |
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Fully Depleted SOI MOSFETs |
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520 | (3) |
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523 | (6) |
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Fully Depleted Collector Mode |
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524 | (2) |
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Partially Depleted Collector Mode |
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526 | (1) |
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Accumulation Collector Mode |
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527 | (1) |
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527 | (2) |
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529 | (9) |
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An Analytic Drain Current Model for Symmetric DG MOSFETs |
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529 | (4) |
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The Scale Length of Double-Gate MOSFETs |
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533 | (1) |
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Fabrication Requirements and Challenges of DG MOSFETs |
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534 | (2) |
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536 | (1) |
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537 | (1) |
Appendix 1 CMOS Process Flow |
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538 | (4) |
Appendix 2 Outline of a Process for Fabricating Modern n-p-n Bipolar Transistors |
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542 | (1) |
Appendix 3 Einstein Relations |
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543 | (3) |
Appendix 4 Spatial Variation of Quasi-Fermi Potentials |
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546 | (7) |
Appendix 5 Generation and Recombination Processes and Space-Charge-Region Current |
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553 | (9) |
Appendix 6 Diffusion Capacitance of a p-n Diode |
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562 | (7) |
Appendix 7 Image-Force-Induced Barrier Lowering |
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569 | (4) |
Appendix 8 Electron-Initiated and Hole-Initiated Avalanche Breakdown |
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573 | (2) |
Appendix 9 An Analytical Solution for the Short-Channel Effect in Subthreshold |
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575 | (7) |
Appendix 10 Generalized MOSFET Scale Length Model |
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582 | (6) |
Appendix 11 Drain Current Model of a Ballistic MOSFET |
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588 | (6) |
Appendix 12 Quantum-Mechanical Solution in Weak Inversion |
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594 | (4) |
Appendix 13 Power Gain of a Two-Port Network |
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598 | (3) |
Appendix 14 Unity-Gain Frequencies of a MOSFET Transistor |
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601 | (4) |
Appendix 15 Determination of Emitter and Base Series Resistances |
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605 | (5) |
Appendix 16 Intrinsic-Base Resistance |
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610 | (4) |
Appendix 17 Energy-Band Diagram of a Si-SiGe n-p Diode |
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614 | (3) |
Appendix 18 fT and Fmax of a Bipolar Transistor |
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617 | (6) |
References |
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623 | (21) |
Index |
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644 | |