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Fundamentals of Modern VLSI Devices 2nd Revised edition [Pehme köide]

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, (University of California, San Diego)
  • Formaat: Paperback / softback, 680 pages, kõrgus x laius x paksus: 246x173x31 mm, kaal: 1320 g
  • Ilmumisaeg: 02-May-2013
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1107635713
  • ISBN-13: 9781107635715
Teised raamatud teemal:
Fundamentals of Modern VLSI Devices 2nd Revised editionSuurem pilt
  • Formaat: Paperback / softback, 680 pages, kõrgus x laius x paksus: 246x173x31 mm, kaal: 1320 g
  • Ilmumisaeg: 02-May-2013
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1107635713
  • ISBN-13: 9781107635715
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781107635715.html
Märksõnad:
Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally renowned authors highlight the intricate interdependencies and subtle trade-offs between various practically important device parameters, and provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model and SiGe-base bipolar devices.

Arvustused

'For the past several years, I've taught from Taur and Ning's book because it's best at connecting advanced device physics to real world device, circuit, and system technology. The second edition updates each chapter, adds new chapters on memory and SOI, doubles the number of appendices, and contains all new homework problems. The best book of its kind is now even better.' Mark Lundstrom, Purdue University 'I have taught a few VLSI device courses with the first edition as a textbook. Those were enjoyable experiences and the book was well received by students. Now the second edition comes with timely updates and two new chapters, which continue the tradition of emphasizing the design aspects of modern VLSI devices. I strongly recommend this book as a text or a reference in semiconductor device courses.' Byung-Gook Park, Seoul National University 'Fundamentals of Modern VLSI Devices, by Taur and Ning, has been an important reference text for our graduate semiconductor device physics course at the University of California, Berkeley for several years. It provides a well-written review of the operation of MOSFETs and BJTs. The new edition expands on this by introducing major new topics related to memories, silicon on insulator devices, and scale length and high field modeling as applied to MOSFETs. By including this material, this text is now positioned to be the primary text for typical graduate device physics courses, and will meet the needs of both students and instructors through its combination of detailed, well-written, and easy to follow descriptions of device operation, coupled with exercises and assignments for testing understanding of the relevant course material.' Vivek Subramanian, University of California, Berkeley 'This second edition of Fundamentals of Modern VLSI Devices builds on the tremendous success enjoyed by the original book. It provides well-organized and in-depth discussions on all relevant aspects of modern MOSFET and BJT devices, with an excellent balance of physics and mathematics. Every chapter is revised to reflect advances in VLSI devices in the last 10 years since the publication of the original book. Two new chapters on memory and silicon-on-insulator devices have been included along with nine additional appendixes. The problems at the end of each chapter are carefully designed and serve to help the readers better understand the key concepts.' Wei Lu, University of Michigan

Muu info

An updated edition of a classic, invaluable for both practical transistor design and teaching.
Preface to the first edition xi
Preface to the second edition xiii
Physical constants and unit conversions xv
List of symbols
xvi
1 Introduction
1(10)
1.1 Evolution of VLSI Device Technology
1(3)
1.1.1 Historical Perspective
1(3)
1.1.2 Recent Developments
4(1)
1.2 Modern VLSI Devices
4(2)
1.2.1 Modern CMOS Transistors
4(1)
1.2.2 Modern Bipolar Transistors
5(1)
1.3 Scope and Brief Description of the Book
6(5)
2 Basic Device Physics
11(137)
2.1 Electrons and Holes in Silicon
11(24)
2.1.1 Energy Bands in Silicon
11(6)
2.1.2 n-Type and p-Type Silicon
17(6)
2.1.3 Carrier Transport in Silicon
23(4)
2.1.4 Basic Equations for Device Operation
27(8)
2.2 p-n Junctions
35(37)
2.2.1 Energy-Band Diagrams for a p-n Diode
35(3)
2.2.2 Abrupt Junctions
38(8)
2.2.3 The Diode Equation
46(5)
2.2.4 Current-Voltage Characteristics
51(13)
2.2.5 Time-Dependent and Switching Characteristics
64(6)
2.2.6 Diffusion Capacitance
70(2)
2.3 MOS Capacitors
72(36)
2.3.1 Surface Potential: Accumulation, Depletion, and Inversion
72(6)
2.3.2 Electrostatic Potential and Charge Distribution in Silicon
78(7)
2.3.3 Capacitances in an MOS Structure
85(6)
2.3.4 Polysilicon-Gate Work Function and Depletion Effects
91(3)
2.3.5 MOS under Nonequilibrium and Gated Diodes
94(4)
2.3.6 Charge in Silicon Dioxide and at the Silicon-Oxide Interface
98(5)
2.3.7 Effect of Interface Traps and Oxide Charge on Device Characteristics
103(5)
2.4 Metal-Silicon Contacts
108(14)
2.4.1 Static Characteristics of a Schottky Barrier Diode
108(7)
2.4.2 Current Transport in a Schottky Barrier Diode
115(1)
2.4.3 Current-Voltage Characteristics of a Schottky Barrier Diode
115(5)
2.4.4 Ohmic Contacts
120(2)
2.5 High-Field Effects
122(26)
2.5.1 Impact Ionization and Avalanche Breakdown
122(3)
2.5.2 Band-to-Band Tunneling
125(2)
2.5.3 Tunneling into and through Silicon Dioxide
127(6)
2.5.4 Injection of Hot Carriers from Silicon into Silicon Dioxide
133(2)
2.5.5 High-Field Effects in Gated Diodes
135(2)
2.5.6 Dielectric Breakdown
137(4)
Exercises
141(7)
3 MOSFET Devices
148(56)
3.1 Long-Channel MOSFETs
148(27)
3.1.1 Drain-Current Model
149(6)
3.1.2 MOSFET I-V Characteristics
155(8)
3.1.3 Subthreshold Characteristics
163(3)
3.1.4 Substrate Bias and Temperature Dependence of Threshold Voltage
166(3)
3.1.5 MOSFET Channel Mobility
169(3)
3.1.6 MOSFET Capacitances and Inversion-Layer Capacitance Effect
172(3)
3.2 Short-Channel MOSFETs
175(29)
3.2.1 Short-Channel Effect
176(10)
3.2.2 Velocity Saturation and High-Field Transport
186(9)
3.2.3 Channel Length Modulation
195(1)
3.2.4 Source-Drain Series Resistance
196(1)
3.2.5 MOSFET Degradation and Breakdown at High Fields
196(5)
Exercises
201(3)
4 CMOS Device Design
204(52)
4.1 MOSFET Scaling
204(8)
4.1.1 Constant-Field Scaling
204(3)
4.1.2 Generalized Scaling
207(3)
4.1.3 Nonscaling Effects
210(2)
4.2 Threshold Voltage
212(30)
4.2.1 Threshold-Voltage Requirement
213(4)
4.2.2 Channel Profile Design
217(7)
4.2.3 Nonuniform Doping
224(10)
4.2.4 Quantum Effect on Threshold Voltage
234(5)
4.2.5 Discrete Dopant Effects on Threshold Voltage
239(3)
4.3 MOSFET Channel Length
242(14)
4.3.1 Various Definitions of Channel Length
242(2)
4.3.2 Extraction of the Effective Channel Length
244(4)
4.3.3 Physical Meaning of Effective Channel Length
248(4)
4.3.4 Extraction of Channel Length by C-V Measurements
252(2)
Exercises
254(2)
5 CMOS Performance Factors
256(62)
5.1 Basic CMOS Circuit Elements
256(17)
5.1.1 CMOS Inverters
256(10)
5.1.2 CMOS NAND and NOR Gates
266(4)
5.1.3 Inverter and NAND Layouts
270(3)
5.2 Parasitic Elements
273(16)
5.2.1 Source-Drain Resistance
274(3)
5.2.2 Parasitic Capacitances
277(3)
5.2.3 Gate Resistance
280(3)
5.2.4 Interconnect R and C
283(6)
5.3 Sensitivity of CMOS Delay to Device Parameters
289(18)
5.3.1 Propagation Delay and Delay Equation
289(7)
5.3.2 Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness
296(3)
5.3.3 Sensitivity of Delay to Power-Supply Voltage and Threshold Voltage
299(2)
5.3.4 Sensitivity of Delay to Parasitic Resistance and Capacitance
301(3)
5.3.5 Delay of Two-Way NAND and Body Effect
304(3)
5.4 Performance Factors of Advanced CMOS Devices
307(11)
5.4.1 MOSFETs in RF Circuits
308(3)
5.4.2 Effect of Transport Parameters on CMOS Performance
311(1)
5.4.3 Low-Temperature CMOS
312(3)
Exercises
315(3)
6 Bipolar Devices
318(56)
6.1 n-p-n Transistors
318(9)
6.1.1 Basic Operation of a Bipolar Transistor
322(1)
6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors
322(5)
6.2 Ideal Current-Voltage Characteristics
327(10)
6.2.1 Collector Current
329(1)
6.2.2 Base Current
330(4)
6.2.3 Current Gains
334(2)
6.2.4 Ideal Ic-VCe Characteristics
336(1)
6.3 Characteristics of a Typical n-p-n Transistor
337(15)
6.3.1 Effect of Emitter and Base Series Resistances
338(2)
6.3.2 Effect of Base-Collector Voltage on Collector Current
340(3)
6.3.3 Collector Current Falloff at High Currents
343(4)
6.3.4 Nonideal Base Current at Low Currents
347(5)
6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses
352(14)
6.4.1 Basic dc Model
352(3)
6.4.2 Basic ac Model
355(1)
6.4.3 Small-Signal Equivalent-Circuit Model
356(3)
6.4.4 Emitter Diffusion Capacitance
359(2)
6.4.5 Charge-Control Analysis
361(5)
6.5 Breakdown Voltages
366(8)
6.5.1 Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche
367(2)
6.5.2 Saturation Currents in a Transistor
369(1)
6.5.3 Relation Between BVCEO and BVCBO
370(1)
Exercises
371(3)
7 Bipolar Device Design
374(63)
7.1 Design of the Emitter Region
374(3)
7.1.1 Diffused or Implanted-and-Diffused Emitter
375(1)
7.1.2 Polysilicon Emitter
376(1)
7.2 Design of the Base Region
377(8)
7.2.1 Relationship between Base Sheet Resistivity and Collector Current Density
378(2)
7.2.2 Intrinsic-Base Dopant Distribution
380(1)
7.2.3 Electric Field in the Quasineutral Intrinsic Base
381(3)
7.2.4 Base Transit Time
384(1)
7.3 Design of the Collector Region
385(4)
7.3.1 Collector Design When There Is Negligible Base Widening
387(1)
7.3.2 Collector Design When There Is Appreciable Base Widening
388(1)
7.4 SiGe-Base Bipolar Transistors
389(40)
7.4.1 Transistors Having a Simple Linearly Graded Base Bandgap
390(6)
7.4.2 Base Current When Ge Is Present in the Emitter
396(5)
7.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base
401(5)
7.4.4 Transistors Having a Constant Ge Distribution in the Base
406(4)
7.4.5 Effect of Emitter Depth Variation on Device Characteristics
410(4)
7.4.6 Some Optimal Ge Profiles
414(5)
7.4.7 Base-Width Modulation by VBE
419(4)
7.4.8 Reverse-Mode I-V Characteristics
423(3)
7.4.9 Heterojunction Nature of a SiGe-Base Bipolar Transistor
426(3)
7.5 Modern Bipolar Transistor Structures
429(8)
7.5.1 Deep-Trench Isolation
429(1)
7.5.2 Polysilicon Emitter
430(1)
7.5.3 Self-Aligned Polysilicon Base Contact
430(1)
7.5.4 Pedestal Collector
431(1)
7.5.5 SiGe-Base
431(1)
Exercises
432(5)
8 Bipolar Performance Factors
437(39)
8.1 Figures of Merit of a Bipolar Transistor
437(4)
8.1.1 Cutoff Frequency
437(3)
8.1.2 Maximum Oscillation Frequency
440(1)
8.1.3 Ring Oscillator and Gate Delay
440(1)
8.2 Digital Bipolar Circuits
441(6)
8.2.1 Delay Components of a Logic Gate
442(3)
8.2.2 Device Structure and Layout for Digital Circuits
445(2)
8.3 Bipolar Device Optimization for Digital Circuits
447(10)
8.3.1 Design Points for a Digital Circuit
447(1)
8.3.2 Device Optimization When There Is Significant Base Widening
448(1)
8.3.3 Device Optimization When There Is Negligible Base Widening
449(4)
8.3.4 Device Optimization for Small Power-Delay Product
453(2)
8.3.5 Bipolar Device Optimization from Some Data Analyses
455(2)
8.4 Bipolar Device Scaling for ECL Circuits
457(6)
8.4.1 Device Scaling Rules
458(2)
8.4.2 Limits in Bipolar Device Scaling for ECL Circuits
460(3)
8.5 Bipolar Device Optimization and Scaling for RF and Analog Circuits
463(6)
8.5.1 The Single-Transistor Amplifier
463(1)
8.5.2 Optimizing the Individual Parameters
464(3)
8.5.3 Technology for RF and Analog Bipolar Devices
467(1)
8.5.4 Limits in Scaling Bipolar Transistors for RF and Analog Applications
468(1)
8.6 Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT
469(7)
Exercises
472(4)
9 Memory Devices
476(41)
9.1 Static Random-Access Memory
477(18)
9.1.1 CMOS SRAM Cell
478(8)
9.1.2 Other Bistable MOSFET SRAM Cells
486(1)
9.1.3 Bipolar SRAM Cell
487(8)
9.2 Dynamic Random-Access Memory
495(5)
9.2.1 Basic DRAM Cell and Its Operation
496(3)
9.2.2 Device Design and Scaling Considerations for a DRAM Cell
499(1)
9.3 Nonvolatile Memory
500(17)
9.3.1 MOSFET Nonvolatile Memory Devices
501(6)
9.3.2 Flash Memory Arrays
507(4)
9.3.3 Floating-Gate Nonvolatile Memory Cells
511(3)
9.3.4 Nonvolatile Memory Cells with Charge Stored in Insulator
514(2)
Exercise
516(1)
10 Silicon-on-Insulator Devices
517(106)
10.1 SOI CMOS
517(6)
10.1.1 Partially Depleted SOI MOSFETs
518(2)
10.1.2 Fully Depleted SOI MOSFETs
520(3)
10.2 Thin-Silicon SOI Bipolar
523(6)
10.2.1 Fully Depleted Collector Mode
524(2)
10.2.2 Partially Depleted Collector Mode
526(1)
10.2.3 Accumulation Collector Mode
527(1)
10.2.4 Discussion
527(2)
10.3 Double-Gate MOSFETs
529(94)
10.3.1 An Analytic Drain Current Model for Symmetric DG MOSFETs
529(4)
10.3.2 The Scale Length of Double-Gate MOSFETs
533(1)
10.3.3 Fabrication Requirements and Challenges of DG MOSFETs
534(2)
10.3.4 Multiple-Gate MOSFETs
536(1)
Exercise
537(1)
Appendix 1 CMOS Process Flow
538(4)
Appendix 2 Outline of a Process for Fabricating Modern n-p-n Bipolar Transistors
542(1)
Appendix 3 Einstein Relations
543(3)
Appendix 4 Spatial Variation of Quasi-Fermi Potentials
546(7)
Appendix 5 Generation and Recombination Processes and Space-Charge-Region Current
553(9)
Appendix 6 Diffusion Capacitance of a p-n Diode
562(7)
Appendix 7 Image-Force-Induced Barrier Lowering
569(4)
Appendix 8 Electron-Initiated and Hole-Initiated Avalanche Breakdown
573(2)
Appendix 9 An Analytical Solution for the Short-Channel Effect in Subthreshold
575(7)
Appendix 10 Generalized MOSFET Scale Length Model
582(6)
Appendix 11 Drain Current Model of a Ballistic MOSFET
588(6)
Appendix 12 Quantum-Mechanical Solution in Weak Inversion
594(4)
Appendix 13 Power Gain of a Two-Port Network
598(3)
Appendix 14 Unity-Gain Frequencies of a MOSFET Transistor
601(4)
Appendix 15 Determination of Emitter and Base Series Resistances
605(5)
Appendix 16 Intrinsic-Base Resistance
610(4)
Appendix 17 Energy-Band Diagram of a Si-SiGe n-p Diode
614(3)
Appendix 18 fT and fmax of a Bipolar Transistor
617(6)
References 623(21)
Index 644
Yuan Taur is a Professor of Electrical and Computer Engineering at the University of California, San Diego. He spent twenty years at IBM's T. J. Watson Research Center where he won numerous invention and achievement awards. He is an IEEE Fellow, Editor-in-Chief of IEEE Electron Device Letters, and holds thirteen US patents. Tak H. Ning is an IBM Fellow at the T. J. Watson Research Center, New York, where he has worked for over 35 years. A Fellow of the IEEE and the American Physical Society and a member of the US National Academy of Engineering, he has authored more than 120 technical papers and holds 36 US patents. He has won several awards, including the ECS 2007 Gordon E. Moore Medal, the IEEE 1991 Jack A. Morton Award and the 1998 Pan Wen-Yuan Foundation Outstanding Research Award.