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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis 2012 [Kõva köide]

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  • Formaat: Hardback, 170 pages, kõrgus x laius: 235x155 mm, kaal: 459 g, XXII, 170 p., 1 Hardback
  • Ilmumisaeg: 21-Oct-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461408717
  • ISBN-13: 9781461408710
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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis 2012Suurem pilt
  • Formaat: Hardback, 170 pages, kõrgus x laius: 235x155 mm, kaal: 459 g, XXII, 170 p., 1 Hardback
  • Ilmumisaeg: 21-Oct-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1461408717
  • ISBN-13: 9781461408710
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781461408710.html
Märksõnad:

This book presents fresh research techniques, algorithms, methodologies and experimental results for high-level power estimation and power-aware high-level synthesis. The book will help get products to market quicker and facilitate low-power ASIC/FPGA design.



This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
1 Introduction
1(12)
1.1 Trends in System Design with System Level Modeling and High Level Synthesis
2(5)
1.1.1 The Need for High Level Synthesis
3(1)
1.1.2 Low Power Design and High Level Modeling
4(1)
1.1.3 Current Power Aware Design Methodology at the High Level
5(1)
1.1.4 Our Power Aware Design Methodology at the High Level
6(1)
1.2 Overview of the Proposed Solutions
7(3)
1.2.1 Application of the Proposed Techniques
9(1)
1.3 Book Organization
10(3)
2 Related Work
13(18)
2.1 High Level Power Estimation
13(5)
2.1.1 Spreadsheet Based Approaches
13(1)
2.1.2 Power Estimation Approaches Utilizing Power Models
14(1)
2.1.3 Power Macro-Model Based Approach
15(2)
2.1.4 Summary of Power Estimation Research
17(1)
2.2 High Level Synthesis
18(6)
2.2.1 High Level Synthesis from C/C++ Specifications
19(3)
2.2.2 High Level Synthesis from Behavioral Specifications
22(1)
2.2.3 Summary of HLS Research
23(1)
2.3 Power Reduction at the RTL and High Level
24(7)
2.3.1 Summary: Low-Power High-Level Synthesis Work
28(3)
3 Background
31(14)
3.1 Average Power Components
31(1)
3.2 PowerTheater
32(1)
3.3 FSMD Modeling Using GEZEL
33(1)
3.3.1 An Example
33(1)
3.4 ESTEREL
34(1)
3.4.1 Esterel Studio
34(1)
3.5 Multivariate Least Squares Linear Regression Model
35(1)
3.5.1 Theoretical Model
35(1)
3.6 Transaction-Level Modeling
36(2)
3.7 High Level Synthesis Using C2R
38(2)
3.8 Power Reduction Using Clock-Gating
40(5)
3.8.1 Clock-Gating
40(1)
3.8.2 Sequential Clock-Gating
41(4)
4 Architectural Selection Using High Level Synthesis
45(14)
4.1 Advance Encryption Standard (AES)
46(2)
4.2 Architectural Exploration for Efficient Hardware Generation
48(4)
4.2.1 AES Restructuring Iterations
48(3)
4.2.2 Results
51(1)
4.3 Functional Verification/Simulation at High-Level
52(4)
4.3.1 Guidelines for Simulation
52(3)
4.3.2 Advantages of C-based Verification Model
55(1)
4.4 Conclusions
56(3)
5 Statistical Regression Based Power Models
59(12)
5.1 Regression Based Power Model for FSMDs
61(1)
5.2 Steps for Power Modeling
62(3)
5.2.1 Learning Phase
63(1)
5.2.2 Utilization Phase
64(1)
5.3 Results and Conclusions
65(6)
5.3.1 Tool Flow
65(1)
5.3.2 Experimental Results
65(3)
5.3.3 Discussion
68(3)
6 Coprocessor Design Space Exploration Using High Level Synthesis
71(10)
6.1 Introduction
71(1)
6.2 Related Work
72(1)
6.3 Methodology
73(3)
6.4 Case Studies and Results
76(5)
6.4.1 Fibonacci and Caesar
76(1)
6.4.2 Bitcounter IP
77(2)
6.4.3 AES
79(2)
7 Regression-Based Dynamic Power Estimation for FPGAs
81(12)
7.1 Introduction
81(1)
7.2 Related Work
82(1)
7.3 FPGA Power Models Using Linear Regression
83(1)
7.4 Methodology
84(3)
7.4.1 Nature of the IPs Used
86(1)
7.4.2 Dynamic Power Evaluation for Reference Model
86(1)
7.4.3 Toggle and Resource Utilization Information
86(1)
7.4.4 Statistical Analysis Using JMP
87(1)
7.4.5 Model Evaluation Phase
87(1)
7.5 Results
87(6)
7.5.1 Varying Data Patterns for Fixed IP Set
88(1)
7.5.2 Varying IPs for Fixed Data Pattern
89(2)
7.5.3 IP Grouping to Increase Accuracy
91(2)
8 High Level Simulation Directed RTL Power Estimation
93(12)
8.1 Introduction
93(1)
8.1.1 Our Approach
94(1)
8.2 Rationale for Our Approach
94(2)
8.3 Our Methodology
96(5)
8.3.1 Activity Extraction from the High-Level VCD
98(1)
8.3.2 High-Level Variable to RTL Signal Mapping
99(2)
8.4 Results
101(4)
9 Applying Verification Collaterals for Accurate Power Estimation
105(14)
9.1 Introduction
105(1)
9.2 Our Methodology
106(4)
9.2.1 Assertions for Finding out Particular Mode of Design
108(1)
9.2.2 Extraction of Modes from the Simulation Dump
109(1)
9.2.3 High-Level Power Estimation
109(1)
9.3 Case Study
110(6)
9.3.1 PSM Specification
110(2)
9.3.2 Directed Testbench Creation from the Specification
112(1)
9.3.3 Utilizing Assertions for Creating Directed Testbench
113(3)
9.4 Results
116(3)
10 Power Reduction Using High-Level Clock-Gating
119(12)
10.1 Introduction
119(2)
10.1.1 Main Contributions
121(1)
10.2 Why is Clock-Gating Needed at High-level?
121(2)
10.3 How to Enable Clock-Gating at High-Level?
123(4)
10.3.1 Application of Clock-Gating for Various Granularities at the Source-Code Level
123(1)
10.3.2 Priority for Clock-Gating Decisions
124(1)
10.3.3 Algorithm for Enabling Clock-gating in C Based Co-processor Synthesis Framework
125(2)
10.4 Results
127(2)
10.4.1 Clock-Gating Exploration at High-Level
128(1)
10.5 Summary
129(2)
11 Model-Checking to Exploit Sequential Clock-Gating
131(12)
11.1 Introduction
131(2)
11.2 Our Approach and Sample Properties
133(3)
11.2.1 An Illustrative Example
133(1)
11.2.2 Our Approach
134(2)
11.3 Our Proposed Methodology
136(4)
11.3.1 Changes Applied on the RTL Model
137(2)
11.3.2 Automation of the Flow
139(1)
11.4 Results and Conclusions
140(3)
11.4.1 Extending the Framework for HLS
140(3)
12 System Level Simulation Guided Approach for Clock-Gating
143(14)
12.1 Introduction
143(1)
12.2 Power Reduction Model
144(3)
12.2.1 Activity Based Power Reduction Model
145(1)
12.2.2 Power Reduction Model with Technology Specific Information
146(1)
12.3 Rationale for Our Approach
147(2)
12.4 Our Methodology
149(4)
12.4.1 TLM Interface for the Generated CATL SystemC Model
152(1)
12.5 Results
153(4)
13 Conclusions
157(6)
13.1 Future Work
160(3)
References 163