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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis 2012 ed. [Pehme köide]

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  • Formaat: Paperback / softback, 170 pages, kõrgus x laius: 235x155 mm, kaal: 454 g, XXII, 170 p., 1 Paperback / softback
  • Ilmumisaeg: 23-Oct-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1489987800
  • ISBN-13: 9781489987808
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  • Pehme köide
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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis 2012 ed.Suurem pilt
  • Formaat: Paperback / softback, 170 pages, kõrgus x laius: 235x155 mm, kaal: 454 g, XXII, 170 p., 1 Paperback / softback
  • Ilmumisaeg: 23-Oct-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1489987800
  • ISBN-13: 9781489987808
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781489987808.html
Märksõnad:

This book presents fresh research techniques, algorithms, methodologies and experimental results for high-level power estimation and power-aware high-level synthesis. The book will help get products to market quicker and facilitate low-power ASIC/FPGA design.



This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.