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Low Power and Reliable SRAM Memory Cell and Array Design 2011 ed. [Kõva köide]

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  • Formaat: Hardback, 144 pages, kõrgus x laius: 235x155 mm, kaal: 407 g, XII, 144 p., 1 Hardback
  • Sari: Springer Series in Advanced Microelectronics 31
  • Ilmumisaeg: 18-Aug-2011
  • Kirjastus: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
  • ISBN-10: 3642195679
  • ISBN-13: 9783642195679
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Low Power and Reliable SRAM Memory Cell and Array Design 2011 ed.Suurem pilt
  • Formaat: Hardback, 144 pages, kõrgus x laius: 235x155 mm, kaal: 407 g, XII, 144 p., 1 Hardback
  • Sari: Springer Series in Advanced Microelectronics 31
  • Ilmumisaeg: 18-Aug-2011
  • Kirjastus: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
  • ISBN-10: 3642195679
  • ISBN-13: 9783642195679
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783642195679.html
Märksõnad:
Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.

The recent development of advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses issues in the design of SRAM memory cells for advanced CMOS technology, including variability, leakage and reliability.
1 Introduction
1(4)
Koichiro Ishibashi
1.1 History and Trend of SRAM Memory Cell
1(2)
1.2 Memory Cell Design Techniques and Array Design Techniques
3(2)
References
4(1)
2 Fundamentals of SRAM Memory Cell
5(6)
Kenichi Osada
2.1 SRAM Cell
5(1)
2.2 Basic Operation of SRAM Cell
5(4)
2.3 Electrical Stability at Read Operation: Static Noise Margin and β Ratio
9(2)
Reference
10(1)
3 Electrical Stability (Read and Write Operations)
11(14)
Masanao Yamaoka
Yasumasa Tsukamoto
3.1 Fundamentals of Electrical Stability on Read and Write Operations
11(5)
3.2 Vth Window Curve
16(3)
3.3 Sensitivity Analysis
19(6)
References
24(1)
4 Low Power Memory Cell Design Technique
25(18)
Kenichi Osada
Masanao Yamaoka
4.1 Fundamentals of Leakage of SRAM Array
25(4)
4.1.1 Leakage Currents in an SRAM of Conventional Design
26(1)
4.1.2 Gate-Tunnel Leakage and GIDL Currents
26(3)
4.2 Source Line Voltage Control Technique
29(7)
4.2.1 EFR Scheme for Low Power SRAM
29(1)
4.2.2 Chip Architecture
29(2)
4.2.3 Results
31(1)
4.2.4 Source Line Voltage Control Technique for SRAM Embedded in the Application Processor
32(4)
4.3 LS-Cell Design for Low-Voltage Operation
36(7)
4.3.1 Lithographically Symmetrical Memory Cell
37(3)
References
40(3)
5 Low-Power Array Design Techniques
43(46)
Koji Nii
Masanao Yamaoka
Kenichi Osada
5.1 Dummy Cell Design
45(9)
5.1.1 Problem with Wide-Voltage Operation
45(1)
5.1.2 Block Diagram and Operation of Voltage-Adapted Timing-Generation Scheme
46(2)
5.1.3 Timing Diagram and Effect of Voltage-Adapted Timing-Generation Scheme
48(2)
5.1.4 Predecoder and Word-Driver Circuits
50(1)
5.1.5 Results
51(3)
5.2 Array Boost Technique
54(5)
5.3 Read and Write Stability Assisting Circuits
59(15)
5.3.1 Concept of Improving Read Stability
59(3)
5.3.2 Variation Tolerant Read Assist Circuits
62(5)
5.3.3 Variation Tolerant Write Assist Circuits
67(4)
5.3.4 Simulation Result
71(1)
5.3.5 Fabrications and Evaluations in 45-nm Technology
72(2)
5.4 Dual-Port Array Design Techniques
74(15)
5.4.1 Access Conflict Issue of Dual-Port SRAM
74(2)
5.4.2 Circumventing Access Scheme of Simultaneous Common Row Activation
76(4)
5.4.3 8T Dual-Port Cell Design
80(1)
5.4.4 Simulated Butterfly Curves for SNM
81(2)
5.4.5 Cell Stability Analysis
83(1)
5.4.6 Standby Leakage
84(1)
5.4.7 Design and Fabrication of Test Chip
84(2)
5.4.8 Measurement Result
86(1)
References
87(2)
6 Reliable Memory Cell Design for Environmental Radiation-Induced Failures in SRAM
89(36)
Eishi Ibe
Kenichi Osada
6.1 Fundamentals of SER in SRAM Cell
90(4)
6.2 SER Caused by Alpha Particle
94(3)
6.3 SER Caused by Neutrons and Its Quantification
97(8)
6.3.1 Basic Knowledge of Terrestrial Neutrons
97(2)
6.3.2 Overall System to Quantify SER-SECIS
99(1)
6.3.3 Simulation Techniques to Quantify Neutron SER
99(3)
6.3.4 Predictions of Scaling Effects from CORIMS
102(3)
6.4 Evolution of MCU Problems and Clarification of the Mechanism
105(10)
6.4.1 MCU Characterization by Accelerator-Based Experiments
105(3)
6.4.2 Simplified 3D Device Simulation Mixed with Circuit Simulation
108(4)
6.4.3 Full 3D Device Simulation with Four-Partial-Cell Model and Multi-Coupled Bipolar Interaction (MCBI)
112(3)
6.5 Countermeasures for Reliable Memory Design
115(10)
6.5.1 ECC Error Correction and Interleave Technique for MCU
115(2)
6.5.2 ECC Architecture
117(1)
6.5.3 Results
118(1)
References
119(6)
7 Future Technologies
125(14)
Koji Nii
Masanao Yamaoka
7.1 7T, 8T, 10T SRAM Cell
125(3)
7.2 Thin-Box FD-SOI SRAM
128(7)
7.3 SRAM Cells for FINFET
135(4)
References
137(2)
Index 139