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Microprogrammed State Machine Design [Kõva köide]

(University of Florida, Gainesville, USA)
  • Formaat: Hardback, 512 pages, kõrgus x laius: 254x178 mm, kaal: 1106 g
  • Ilmumisaeg: 12-Jan-1993
  • Kirjastus: CRC Press Inc
  • ISBN-10: 0849344646
  • ISBN-13: 9780849344640
  • Formaat: Hardback, 512 pages, kõrgus x laius: 254x178 mm, kaal: 1106 g
  • Ilmumisaeg: 12-Jan-1993
  • Kirjastus: CRC Press Inc
  • ISBN-10: 0849344646
  • ISBN-13: 9780849344640
Microprogrammed State Machine Design is a digital computer architecture text that builds systematically from basic concepts to complex state-machine design. It provides practical techniques and alternatives for designing solutions to data processing problems both in commerce and in research purposes. It offers an excellent introduction to the tools and elements of design used in microprogrammed state machines, and incoporates the necessary background in number systems, hardware building blocks, assemblers for use in preparing control programs, and tools and components for assemblers .

The author conducts an in-depth examination of first- and second-level microprogrammed state machines. He promotes a top-down approach that examines algorithms mathematically to exploit the simplifications resulting from choosing the proper representation and application of algebraic manipulation. The steps involved in the cycle of design and simulation steps are demonstrated through an example of running a computer through a simulation.

Other topics covered in Microprogrammed State Machine Design include a discussion of simulation methods, the development and use of assembler language processors, and comparisons among various hardware implementations, such as the Reduced Instruction Set Computer (RISC) and the Digital Signal Processor (DSP).

As a text and guide, Microprogrammed State Machine Design will interest students in the computer sciences, computer architectects and engineers, systems programmers and analysts, and electrical engineers.

Arvustused

"An excellent introduction to problem solving, discrete versus continuous solutions, algorithms versus equations, Moore and Mealy machines...text is written in a clear, pleasant, easy-to-follow style...the book flows nicely." -Eugene Fabricious, California Polytechnic State University-San Louis Obispo

Introduction
1(16)
Goals
1(1)
The Problem
1(1)
The Solution
2(6)
Solution--Continuous or Discrete?
3(1)
Solution--Continuous
3(1)
Solution--Discrete
4(1)
Discrete Data
4(1)
Systems Having Continuous Time
5(1)
Systems Having Discrete Time
6(1)
Repetition and Iteration
7(1)
The Algorithmic State Machine
8(2)
The Instruction Set Processor
10(7)
Exercise
13(4)
Representation of Numbers
17(18)
Introduction
17(1)
Representation of Integers
17(3)
Unsigned Binary Integers
17(1)
Signed Binary Integers
18(1)
Two's Complement Signed Binary Integers
18(2)
Addition of Signed and Unsigned Binary Numbers
20(3)
Overflow
21(2)
Two's Complement and Sign/Magnitude Conversion
23(1)
Subtraction of Signed and Unsigned Binary Integers
23(1)
Encoded Binary Notations
24(1)
Fixed Point Representation
25(3)
The Floating Point Representation
28(7)
The IEEE 754 Floating Point Representation
29(2)
Floating Point Addition and Subtraction
31(1)
Floating Point Multiplication
32(1)
Floating Point Overflow
32(1)
Summary of the Floating Point Representation
33(1)
Exercises
33(2)
Architectural Components
35(52)
Introduction
35(1)
Review of Basic Digital Elements
35(2)
Simple Combinatorial Structures
37(2)
The Simplest Arithmetic Structure---The Adder
39(1)
Combinations of Simple Networks
40(10)
The Multibit Full Adder
41(4)
The Shifter
45(1)
The Arithmetic/Logic Unit (ALU)
46(4)
Memory Elements
50(8)
Flip-Flops
50(2)
Registers
52(3)
Complex Register Structures
55(3)
Complex Architectures
58(8)
The Accumulator
58(2)
The Register Arithmetic/Logic Unit (RALU)
60(2)
Real RALUs
62(4)
Table-Driven Arithmetic Operations
66(2)
Multiplication
68(2)
Floating Point Arithmetic Units
70(3)
Some Real Architectural Units
73(14)
Real Register Arithmetic Logic Units
73(2)
Real Integer Multipliers and MACs
75(1)
Real Floating Point Units
76(9)
Exercises
85(2)
Controllers
87(34)
Introduction
87(1)
Algorithmic State Machine Design
87(3)
ROM-Latch Microprogrammed ASM Implementation
90(4)
Counter-Based Microprogrammed ASM Implementation
94(7)
Register-Based Advanced Microprogrammed Controllers
101(8)
Register-Based Controller with All the Bells and Whistles
109(2)
Integrated Circuit Microprogrammed Controllers
111(10)
Examples of the Next Address Generator
111(4)
Integrated Microprogrammed Controllers
115(5)
Exercises
120(1)
Assemblers
121(46)
Introduction
121(1)
The Microprogram Word
121(2)
The Symbolic Microinstruction Format
123(2)
The Definition Process
125(5)
The Assembly Process
130(1)
Operation of the Microcode Assember System
131(3)
An Assembler for the Second-level Machine---Introduction
134(1)
The Format of an Assembler Language Statement
135(1)
Assembler Implementation Methods
135(1)
The Cross Assembler
136(1)
An Assembler Algorithm Detail
137(1)
Method Used to Adapt a Macroassembler
138(2)
Extended Use of Macros
140(1)
Placing the Assembler Program in the Target ISP
141(3)
A Shareware Assembler
144(9)
Examples of Microcoding with A68K
145(7)
Examples Showing A68K Used as a Second--Level Cross Assembler
152(1)
Conclusion
153(14)
Appendix A. User's Manual for the Microtec Meta Assembler
154(1)
Directives
154(1)
Symbol Specification
155(1)
Constants
155(1)
Variables
156(1)
Appendix B. User's Manual for the Modified A68K Macro Cross Assembler
156(1)
Introduction
156(1)
Symbols
156(1)
Constants
156(1)
Comments
157(1)
Assembler Directives
157(3)
Expressions
160(1)
Special Symbols
161(1)
Appendix C. Data Transmission Formats for Object Files
162(1)
Motorola S-Record Format
162(1)
The Intel Hex Format
162(1)
Exercises
163(4)
Hardware Description Language and Simulation
167(62)
Introduction
167(2)
Program Design Language
169(1)
Hardware Description Language
170(7)
Simulation of the Second Level of Control
177(6)
The Fetch/Execute Cycle--Based Simulator
178(1)
Macro-Based Simulator
179(4)
Simulation of the First Level of Control
183(39)
The Hardware Description Language as a Simulator
183(3)
Behavioral Simulation of Architectural Components
186(1)
Simulation of Registers and Memory
187(1)
Simulation of Buses
188(2)
Simulation of Combinational Elements
190(7)
Simulation of An RALU
197(2)
Simulation of Controllers
199(5)
Complete Algorithmic State Machine Simulations
204(1)
A Simple RALU Driven by a Table-Based Controller
204(3)
Simulation of the Basic Computer Example
207(3)
Interconnection of IC Simulation Modules Using Pointer Arrays
210(9)
Simulation of the Electrical Behavior of Architectures
219(1)
Critical Path Determination
219(2)
Output Loading
221(1)
Conclusion
222(7)
Exercises
223(6)
Algorithms and Architectures
229(76)
Introduction
229(1)
Designs Using One Level of Control
229(51)
Some Introductory Designs
230(21)
Accumulation
251(6)
Multiplication of Unsinged Binary Numbers
257(4)
Multiplication of Two's Complement Binary Numbers
261(4)
Division of Unsigned Binary Numbers
265(1)
Table Look--Up
265(1)
Restoring Division Algorithm-Conditional Subtract and Shift
266(3)
Non-Restoring Division
269(5)
The Arithmetic Sum of Products
274(4)
The Power Series Expansion
278(2)
Replacement of Algorithmic Modules by Combinatorial Modules
280(2)
Coprocessors
282(9)
Memory-Mapped Coprocessor
283(5)
Independent Coprocessors
288(3)
A Final Example
291(8)
Conclusion
299(6)
Exercises
299(1)
Procedure
300(1)
Design Exercises
301(4)
A Microprogrammed Computer
305(122)
Introduction
305(1)
Basic Architecture
305(2)
The Instruction Set
305(1)
The Addressing Modes
306(1)
The Programming Model
307(1)
The Second-Level Machine Instruction Format
307(2)
Major Logical Sections of the Computer
309(2)
Physical Implementation of the Computer Example
311(7)
Implementation of the First-Level Machine
318(1)
Some Important Sequences
319(12)
The Reset Sequence
319(1)
The Instruction Fetch Sequence
320(1)
The Basic Address Mode Sequences
321(3)
Additional Address Modes
324(2)
Dealing with the Microword Symbolically
326(2)
Execution Sequences
328(3)
Conclusion
331(96)
Exercises
332(9)
Appendices to
Chapter 8
Detailed Description of the Basic Computer Example
341(1)
Appendix A. Computer Example--Microcode Bit Field Definitions
342(4)
Pipeline Format-Each Microword
346(1)
Appendix B. Computer Example--Multiplexer Select Definitions
347(3)
Appendix C. Parsed Microcode Display
350(3)
Appendix D. Instruction Set Reference
353(3)
Sweet/16 Instruction Set User's Manual
356(11)
Appendix E1. Sweet 16 Macro Definition File
367(10)
Appendix E2. Sweet 16 MONITOR Program
377(17)
Appendix F. Sweet 16 MONITOR Object Code in Intel HEX Format
394(1)
MON.H-Upper byte of each word with checksum
394(1)
MON.L-Lower byte of each word
394(1)
SW16TEST-Example test program machine code in Intel HEX Format
395(1)
Appendix G. First-Level Definition File for Basic Computer Example
396(5)
Appendix H. First-Level Source Program for the Basic Computer Example
401(14)
Appendix I. Demonstration
415(12)
Improvements, Variations, and Conclusion
427(52)
Introduction
427(1)
Improvements
428(27)
The Memory Address Register Bus
428(2)
Byte/Word Addressing
430(5)
Interrupts to the Second Level of Control
435(11)
Memory Access by Controllers other than the CPU
446(5)
Instruction and Data Pipelines and Caching
451(4)
Variations
455(18)
Traditional Controller Implementation
456(2)
Reduced Instruction Set Computer (RISC) Architecture
458(4)
Digital Signal Processors (DSP)
462(3)
Video Display Processors
465(3)
Pseudo Second-Level Machine
468(5)
Fabrication Considerations and Conclusion
473(6)
Exercises
475(4)
Bibliography 479(4)
Index 483
Michel A. Lynch