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1 | (16) |
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1 | (1) |
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1 | (1) |
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2 | (6) |
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Solution--Continuous or Discrete? |
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3 | (1) |
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3 | (1) |
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4 | (1) |
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4 | (1) |
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Systems Having Continuous Time |
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5 | (1) |
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Systems Having Discrete Time |
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6 | (1) |
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7 | (1) |
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The Algorithmic State Machine |
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8 | (2) |
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The Instruction Set Processor |
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10 | (7) |
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13 | (4) |
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Representation of Numbers |
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17 | (18) |
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17 | (1) |
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Representation of Integers |
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17 | (3) |
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17 | (1) |
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18 | (1) |
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Two's Complement Signed Binary Integers |
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18 | (2) |
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Addition of Signed and Unsigned Binary Numbers |
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20 | (3) |
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21 | (2) |
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Two's Complement and Sign/Magnitude Conversion |
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23 | (1) |
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Subtraction of Signed and Unsigned Binary Integers |
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23 | (1) |
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24 | (1) |
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Fixed Point Representation |
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25 | (3) |
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The Floating Point Representation |
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28 | (7) |
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The IEEE 754 Floating Point Representation |
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29 | (2) |
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Floating Point Addition and Subtraction |
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31 | (1) |
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Floating Point Multiplication |
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32 | (1) |
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32 | (1) |
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Summary of the Floating Point Representation |
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33 | (1) |
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33 | (2) |
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35 | (52) |
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35 | (1) |
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Review of Basic Digital Elements |
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35 | (2) |
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Simple Combinatorial Structures |
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37 | (2) |
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The Simplest Arithmetic Structure---The Adder |
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39 | (1) |
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Combinations of Simple Networks |
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40 | (10) |
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41 | (4) |
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45 | (1) |
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The Arithmetic/Logic Unit (ALU) |
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46 | (4) |
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50 | (8) |
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50 | (2) |
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52 | (3) |
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Complex Register Structures |
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55 | (3) |
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58 | (8) |
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58 | (2) |
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The Register Arithmetic/Logic Unit (RALU) |
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60 | (2) |
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62 | (4) |
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Table-Driven Arithmetic Operations |
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66 | (2) |
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68 | (2) |
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Floating Point Arithmetic Units |
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70 | (3) |
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Some Real Architectural Units |
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73 | (14) |
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Real Register Arithmetic Logic Units |
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73 | (2) |
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Real Integer Multipliers and MACs |
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75 | (1) |
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Real Floating Point Units |
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76 | (9) |
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85 | (2) |
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87 | (34) |
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87 | (1) |
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Algorithmic State Machine Design |
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87 | (3) |
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ROM-Latch Microprogrammed ASM Implementation |
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90 | (4) |
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Counter-Based Microprogrammed ASM Implementation |
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94 | (7) |
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Register-Based Advanced Microprogrammed Controllers |
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101 | (8) |
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Register-Based Controller with All the Bells and Whistles |
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109 | (2) |
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Integrated Circuit Microprogrammed Controllers |
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111 | (10) |
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Examples of the Next Address Generator |
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111 | (4) |
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Integrated Microprogrammed Controllers |
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115 | (5) |
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120 | (1) |
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121 | (46) |
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121 | (1) |
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121 | (2) |
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The Symbolic Microinstruction Format |
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123 | (2) |
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125 | (5) |
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130 | (1) |
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Operation of the Microcode Assember System |
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131 | (3) |
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An Assembler for the Second-level Machine---Introduction |
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134 | (1) |
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The Format of an Assembler Language Statement |
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135 | (1) |
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Assembler Implementation Methods |
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135 | (1) |
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136 | (1) |
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An Assembler Algorithm Detail |
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137 | (1) |
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Method Used to Adapt a Macroassembler |
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138 | (2) |
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140 | (1) |
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Placing the Assembler Program in the Target ISP |
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141 | (3) |
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144 | (9) |
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Examples of Microcoding with A68K |
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145 | (7) |
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Examples Showing A68K Used as a Second--Level Cross Assembler |
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152 | (1) |
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153 | (14) |
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Appendix A. User's Manual for the Microtec Meta Assembler |
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154 | (1) |
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154 | (1) |
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155 | (1) |
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155 | (1) |
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156 | (1) |
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Appendix B. User's Manual for the Modified A68K Macro Cross Assembler |
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156 | (1) |
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156 | (1) |
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156 | (1) |
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156 | (1) |
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157 | (1) |
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157 | (3) |
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160 | (1) |
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161 | (1) |
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Appendix C. Data Transmission Formats for Object Files |
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162 | (1) |
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162 | (1) |
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162 | (1) |
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163 | (4) |
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Hardware Description Language and Simulation |
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167 | (62) |
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167 | (2) |
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169 | (1) |
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Hardware Description Language |
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170 | (7) |
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Simulation of the Second Level of Control |
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177 | (6) |
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The Fetch/Execute Cycle--Based Simulator |
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178 | (1) |
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179 | (4) |
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Simulation of the First Level of Control |
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183 | (39) |
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The Hardware Description Language as a Simulator |
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183 | (3) |
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Behavioral Simulation of Architectural Components |
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186 | (1) |
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Simulation of Registers and Memory |
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187 | (1) |
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188 | (2) |
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Simulation of Combinational Elements |
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190 | (7) |
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197 | (2) |
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Simulation of Controllers |
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199 | (5) |
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Complete Algorithmic State Machine Simulations |
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204 | (1) |
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A Simple RALU Driven by a Table-Based Controller |
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204 | (3) |
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Simulation of the Basic Computer Example |
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207 | (3) |
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Interconnection of IC Simulation Modules Using Pointer Arrays |
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210 | (9) |
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Simulation of the Electrical Behavior of Architectures |
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219 | (1) |
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Critical Path Determination |
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219 | (2) |
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221 | (1) |
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222 | (7) |
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223 | (6) |
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Algorithms and Architectures |
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229 | (76) |
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229 | (1) |
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Designs Using One Level of Control |
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229 | (51) |
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Some Introductory Designs |
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230 | (21) |
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251 | (6) |
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Multiplication of Unsinged Binary Numbers |
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257 | (4) |
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Multiplication of Two's Complement Binary Numbers |
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261 | (4) |
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Division of Unsigned Binary Numbers |
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265 | (1) |
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265 | (1) |
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Restoring Division Algorithm-Conditional Subtract and Shift |
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266 | (3) |
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269 | (5) |
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The Arithmetic Sum of Products |
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274 | (4) |
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The Power Series Expansion |
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278 | (2) |
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Replacement of Algorithmic Modules by Combinatorial Modules |
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280 | (2) |
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282 | (9) |
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Memory-Mapped Coprocessor |
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283 | (5) |
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288 | (3) |
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291 | (8) |
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299 | (6) |
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299 | (1) |
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300 | (1) |
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301 | (4) |
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A Microprogrammed Computer |
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305 | (122) |
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305 | (1) |
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305 | (2) |
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305 | (1) |
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306 | (1) |
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307 | (1) |
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The Second-Level Machine Instruction Format |
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307 | (2) |
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Major Logical Sections of the Computer |
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309 | (2) |
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Physical Implementation of the Computer Example |
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311 | (7) |
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Implementation of the First-Level Machine |
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318 | (1) |
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319 | (12) |
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319 | (1) |
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The Instruction Fetch Sequence |
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320 | (1) |
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The Basic Address Mode Sequences |
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321 | (3) |
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324 | (2) |
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Dealing with the Microword Symbolically |
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326 | (2) |
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328 | (3) |
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331 | (96) |
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332 | (9) |
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Detailed Description of the Basic Computer Example |
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341 | (1) |
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Appendix A. Computer Example--Microcode Bit Field Definitions |
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342 | (4) |
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Pipeline Format-Each Microword |
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346 | (1) |
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Appendix B. Computer Example--Multiplexer Select Definitions |
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347 | (3) |
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Appendix C. Parsed Microcode Display |
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350 | (3) |
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Appendix D. Instruction Set Reference |
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353 | (3) |
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Sweet/16 Instruction Set User's Manual |
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356 | (11) |
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Appendix E1. Sweet 16 Macro Definition File |
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367 | (10) |
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Appendix E2. Sweet 16 MONITOR Program |
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377 | (17) |
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Appendix F. Sweet 16 MONITOR Object Code in Intel HEX Format |
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394 | (1) |
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MON.H-Upper byte of each word with checksum |
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394 | (1) |
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MON.L-Lower byte of each word |
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394 | (1) |
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SW16TEST-Example test program machine code in Intel HEX Format |
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395 | (1) |
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Appendix G. First-Level Definition File for Basic Computer Example |
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396 | (5) |
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Appendix H. First-Level Source Program for the Basic Computer Example |
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401 | (14) |
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Appendix I. Demonstration |
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415 | (12) |
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Improvements, Variations, and Conclusion |
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427 | (52) |
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427 | (1) |
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428 | (27) |
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The Memory Address Register Bus |
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428 | (2) |
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430 | (5) |
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Interrupts to the Second Level of Control |
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435 | (11) |
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Memory Access by Controllers other than the CPU |
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446 | (5) |
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Instruction and Data Pipelines and Caching |
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451 | (4) |
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455 | (18) |
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Traditional Controller Implementation |
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456 | (2) |
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Reduced Instruction Set Computer (RISC) Architecture |
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458 | (4) |
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Digital Signal Processors (DSP) |
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462 | (3) |
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465 | (3) |
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Pseudo Second-Level Machine |
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468 | (5) |
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Fabrication Considerations and Conclusion |
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473 | (6) |
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475 | (4) |
Bibliography |
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479 | (4) |
Index |
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483 | |