About the Editors |
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Preface |
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Network Processors: Themes and Challenges |
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1 | (8) |
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2 | (1) |
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3 | (2) |
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5 | (1) |
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Challenges and Conclusions |
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6 | (3) |
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7 | (2) |
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9 | (290) |
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A Programmable, Scalable Platform for Next-Generation Networking |
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11 | (18) |
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The Network Processor Architecture |
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14 | (3) |
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17 | (4) |
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Fibre Channel/Infiniband Implementation |
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21 | (2) |
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Performance Simulation and Analysis |
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23 | (3) |
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26 | (3) |
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27 | (1) |
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27 | (2) |
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Power Considerations in Network Processor Design |
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29 | (22) |
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Computational Performance Model |
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32 | (5) |
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37 | (5) |
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42 | (1) |
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43 | (6) |
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49 | (2) |
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49 | (1) |
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49 | (2) |
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Worst-Case Execution Time Estimation for Hardware-Assisted Multithreaded Processors |
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51 | (24) |
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Background and Motivation |
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53 | (2) |
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Processing Throughput of a Single Thread of Execution |
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55 | (4) |
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Processing Throughput of Two Threads |
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59 | (10) |
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Processing Throughput of Four Threads |
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69 | (1) |
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Limitations and Future Work |
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69 | (2) |
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71 | (4) |
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72 | (1) |
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72 | (3) |
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Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas |
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75 | (26) |
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Related Work and Concepts |
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77 | (7) |
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Issues in Using Pfair Schedulers in Routers |
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84 | (3) |
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Multiprocessor Scheduling in Routers: Key Ideas |
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87 | (7) |
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94 | (2) |
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96 | (5) |
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96 | (1) |
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96 | (5) |
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A Massively Multithreaded Packet Processor |
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101 | (32) |
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Random External Memory Accesses |
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104 | (1) |
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Processor/Memory Architectures |
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105 | (2) |
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The Tribe Microarchitecture |
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107 | (13) |
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120 | (4) |
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124 | (4) |
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128 | (1) |
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129 | (4) |
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131 | (2) |
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Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors |
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133 | (26) |
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134 | (3) |
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Performance Modeling and Evaluation |
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137 | (9) |
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Topology Exploration for Performance Metrics |
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146 | (6) |
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Interrelation Between Programmability and Topologies |
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152 | (3) |
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155 | (4) |
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156 | (1) |
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157 | (2) |
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Packet Classification and Termination in a Protocol Processor |
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159 | (22) |
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Programmable Protocol Processor |
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160 | (5) |
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Control Memory Access Accelerator |
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165 | (12) |
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177 | (2) |
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179 | (1) |
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179 | (2) |
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179 | (1) |
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180 | (1) |
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NP-Click: A Programming Model for the Intel IXP1200 |
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181 | (22) |
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182 | (3) |
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185 | (3) |
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188 | (6) |
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194 | (4) |
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198 | (1) |
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199 | (4) |
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200 | (1) |
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200 | (3) |
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Nepal: A Framework for Efficiently Structuring Applications for Network Processors |
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203 | (24) |
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William H. Mangione-Smith |
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206 | (2) |
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208 | (1) |
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Module Extraction from Sequential Binaries |
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209 | (4) |
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213 | (2) |
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215 | (1) |
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216 | (7) |
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223 | (1) |
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224 | (3) |
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225 | (2) |
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Efficient and Faithful Performance Modeling for Network-Processor-Based System Designs |
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227 | (16) |
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Approaches to Performance Modeling |
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229 | (2) |
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Discrete-Event Simulation |
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231 | (1) |
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Application-Hardware Interface |
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232 | (1) |
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Modeling Memory Reference Behavior |
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233 | (1) |
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234 | (1) |
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Modeling Multiple Processors |
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235 | (1) |
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Using Countach for Modeling Network Servers |
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236 | (2) |
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238 | (2) |
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Conclusions and Ongoing Work |
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240 | (3) |
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241 | (2) |
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High-Speed Legitimacy-Based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200 |
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243 | (30) |
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Background: Legitimacy Tests and Legitimacy List Management |
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246 | (8) |
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Prototype Architecture on the Intel IXP1200 Network Processor |
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254 | (4) |
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Performance Analysis Experiments |
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258 | (2) |
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260 | (6) |
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Lessons Learned on Architectural Directions for Network Processors |
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266 | (3) |
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Conclusions and Future Work |
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269 | (4) |
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270 | (1) |
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270 | (3) |
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Directions in Packet Classification for Network Processors |
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273 | (26) |
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275 | (4) |
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279 | (10) |
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Transport-Level Field Analysis |
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289 | (3) |
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292 | (1) |
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293 | (6) |
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Appendix: Derivation of a Tighter Bound on the Number of Partial Overlaps |
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294 | (3) |
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297 | (2) |
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299 | (144) |
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Implementing High-Performance, High-Value Traffic Management Using Agere Network Processor Solutions |
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301 | (26) |
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Implementing Traffic Management |
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302 | (2) |
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304 | (16) |
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320 | (5) |
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325 | (2) |
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326 | (1) |
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AMCC nPcore NISC Architecture |
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327 | (16) |
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The nPcore-based Architecture |
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327 | (12) |
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339 | (2) |
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341 | (2) |
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342 | (1) |
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Adaptable Bandwidth Allocation for QoS Support in Network Processors |
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343 | (22) |
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344 | (6) |
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QoS Design for Network Processors |
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350 | (9) |
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359 | (3) |
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362 | (3) |
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362 | (3) |
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IDT Network Search Engine with QDR LA-1 Interface |
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365 | (20) |
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366 | (6) |
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Development and System Support Tools |
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372 | (3) |
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Database Search Solutions, Analysis and Comparison |
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375 | (8) |
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383 | (2) |
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383 | (2) |
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Implementing Voice over AAL2 on a Network Processor |
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385 | (20) |
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IXP2400 Network Processor |
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386 | (1) |
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Voice Service Requirements |
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387 | (1) |
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387 | (2) |
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Packet Processing in the VoAAL2 Application |
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389 | (2) |
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391 | (2) |
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VoAAL2 Application on IXP2400 |
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393 | (6) |
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Challenges and Lessons Learned |
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399 | (3) |
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402 | (3) |
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403 | (2) |
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Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor |
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405 | (22) |
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The Motorola C-5e Network Processor |
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406 | (1) |
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407 | (9) |
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416 | (8) |
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424 | (1) |
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425 | (2) |
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426 | (1) |
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A C-Based Programming Language for Multiprocessor Network SoC Architectures |
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427 | (16) |
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Software Design Considerations |
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427 | (1) |
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The Teja NP Software Platform |
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428 | (1) |
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The Teja C Programming Language |
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429 | (9) |
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438 | (3) |
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441 | (2) |
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442 | (1) |
Index |
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