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E-raamat: Network Processor Design: Issues and Practices

Edited by (Integrated Device Technology, Inc.), Edited by (Washington University, St. Louis), Edited by (Associate Professor, Computer Science & Engineering, Washington University in St. Louis), Edited by (Polytechnic University, New York)
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Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.

Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.

Muu info

The latest information from the leading network processor designers in research and industry.
About the Editors v
Preface xv
Network Processors: Themes and Challenges
1(8)
Patrick Crowley
Mark A. Franklin
Haldun Hadimioglu
Peter Z. Onufryk
Technology
2(1)
Programming
3(2)
Applications
5(1)
Challenges and Conclusions
6(3)
References
7(2)
PART I DESIGN PRINCIPLES
9(290)
A Programmable, Scalable Platform for Next-Generation Networking
11(18)
Christos J. Georgiou
Valentina Salapura
Monty Denneau
The Network Processor Architecture
14(3)
Processor Scheduling
17(4)
Fibre Channel/Infiniband Implementation
21(2)
Performance Simulation and Analysis
23(3)
Conclusions
26(3)
Acknowledgments
27(1)
References
27(2)
Power Considerations in Network Processor Design
29(22)
Mark A. Franklin
Tilman Wolf
Computational Performance Model
32(5)
Power Model
37(5)
Performance Metrics
42(1)
Design Results
43(6)
Summary and Conclusions
49(2)
Acknowledgments
49(1)
References
49(2)
Worst-Case Execution Time Estimation for Hardware-Assisted Multithreaded Processors
51(24)
Patrick Crowley
Jean-Loup Baer
Background and Motivation
53(2)
Processing Throughput of a Single Thread of Execution
55(4)
Processing Throughput of Two Threads
59(10)
Processing Throughput of Four Threads
69(1)
Limitations and Future Work
69(2)
Conclusions
71(4)
Acknowledgments
72(1)
References
72(3)
Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas
75(26)
Anand Srinivasan
Philip Holman
James Anderson
Sanjoy Baruah
Jasleen Kaur
Related Work and Concepts
77(7)
Issues in Using Pfair Schedulers in Routers
84(3)
Multiprocessor Scheduling in Routers: Key Ideas
87(7)
Experimental Evaluation
94(2)
Conclusions
96(5)
Acknowledgments
96(1)
References
96(5)
A Massively Multithreaded Packet Processor
101(32)
Steve Melvin
Mario Nemirovsky
Enric Musoll
Jeff Huynh
Rodolfo Milito
Hector Urdaneta
Koroush Saraf
Random External Memory Accesses
104(1)
Processor/Memory Architectures
105(2)
The Tribe Microarchitecture
107(13)
Network Block
120(4)
Interconnect
124(4)
Project Status
128(1)
Conclusions
129(4)
References
131(2)
Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors
133(26)
Matthias Gries
Chidamber Kulkarni
Christian Sauer
Kurt Keutzer
Problem Identification
134(3)
Performance Modeling and Evaluation
137(9)
Topology Exploration for Performance Metrics
146(6)
Interrelation Between Programmability and Topologies
152(3)
Conclusions
155(4)
Acknowledgments
156(1)
References
157(2)
Packet Classification and Termination in a Protocol Processor
159(22)
Ulf Nordqvist
Dake Liu
Programmable Protocol Processor
160(5)
Control Memory Access Accelerator
165(12)
System Performance
177(2)
Conclusions
179(1)
Further Work
179(2)
Acknowledgments
179(1)
References
180(1)
NP-Click: A Programming Model for the Intel IXP1200
181(22)
Niraj Shah
William Plishker
Kurt Keutzer
Background
182(3)
Programming Models
185(3)
Description of NP-Click
188(6)
Results
194(4)
Summary and Conclusions
198(1)
Future Work
199(4)
Acknowledgments
200(1)
References
200(3)
Nepal: A Framework for Efficiently Structuring Applications for Network Processors
203(24)
Gokhan Memik
William H. Mangione-Smith
Modules
206(2)
Nepal Design Flow
208(1)
Module Extraction from Sequential Binaries
209(4)
Dynamic Module Manager
213(2)
Discussion
215(1)
Experiments
216(7)
Related Work
223(1)
Conclusions
224(3)
References
225(2)
Efficient and Faithful Performance Modeling for Network-Processor-Based System Designs
227(16)
Prashant Pradhan
Indira Nair
Sambit Sahu
Wen Xu
Approaches to Performance Modeling
229(2)
Discrete-Event Simulation
231(1)
Application-Hardware Interface
232(1)
Modeling Memory Reference Behavior
233(1)
Time Synchronization
234(1)
Modeling Multiple Processors
235(1)
Using Countach for Modeling Network Servers
236(2)
Performance Evaluation
238(2)
Conclusions and Ongoing Work
240(3)
References
241(2)
High-Speed Legitimacy-Based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200
243(30)
Roshan K. Thomas
Brian L. Mark
Tommy O. Johnson
James B. Croall
Background: Legitimacy Tests and Legitimacy List Management
246(8)
Prototype Architecture on the Intel IXP1200 Network Processor
254(4)
Performance Analysis Experiments
258(2)
Performance Results
260(6)
Lessons Learned on Architectural Directions for Network Processors
266(3)
Conclusions and Future Work
269(4)
Acknowledgments
270(1)
References
270(3)
Directions in Packet Classification for Network Processors
273(26)
Michael E. Kounavis
Alok Kumar
Harrick Vin
Raj Yavatkar
Andrew T. Campbell
Problem Formulation
275(4)
IP Prefix Pair Analysis
279(10)
Transport-Level Field Analysis
289(3)
Implications
292(1)
Conclusions
293(6)
Appendix: Derivation of a Tighter Bound on the Number of Partial Overlaps
294(3)
References
297(2)
PART II PRACTICES
299(144)
Implementing High-Performance, High-Value Traffic Management Using Agere Network Processor Solutions
301(26)
Jian-Guo Chen
David Sonnier
Robert Munoz
Vinoj Kumar
Ambalavanar Arulambalam
Implementing Traffic Management
302(2)
10-Gb/s System Solution
304(16)
5-Gb/s APP550 Solution
320(5)
Conclusions
325(2)
References
326(1)
AMCC nPcore NISC Architecture
327(16)
Robin Melnick
Keith Morris
The nPcore-based Architecture
327(12)
Software Architecture
339(2)
Conclusions
341(2)
References
342(1)
Adaptable Bandwidth Allocation for QoS Support in Network Processors
343(22)
Clark Jeffries
Mohammad Peyravian
Ravi Sabhikhi
Background
344(6)
QoS Design for Network Processors
350(9)
IBM PowerNP QoS Support
359(3)
Conclusions
362(3)
References
362(3)
IDT Network Search Engine with QDR LA-1 Interface
365(20)
Michael J. Miller
NSE Device Description
366(6)
Development and System Support Tools
372(3)
Database Search Solutions, Analysis and Comparison
375(8)
Conclusion
383(2)
References
383(2)
Implementing Voice over AAL2 on a Network Processor
385(20)
Jaroslaw Sydir
Prashant Chandra
Alok Kumar
Sridhar Lakshmanamurthy
Longsong Lin
Muthaiah Venkatachalam
IXP2400 Network Processor
386(1)
Voice Service Requirements
387(1)
VoAAL2 Service
387(2)
Packet Processing in the VoAAL2 Application
389(2)
QoS Considerations
391(2)
VoAAL2 Application on IXP2400
393(6)
Challenges and Lessons Learned
399(3)
Conclusions
402(3)
References
403(2)
Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor
405(22)
Pranav Gambhire
The Motorola C-5e Network Processor
406(1)
Implementing ATM QoS
407(9)
Implementing diffserv
416(8)
Design Alternatives
424(1)
Conclusions
425(2)
References
426(1)
A C-Based Programming Language for Multiprocessor Network SoC Architectures
427(16)
Kevin Crozier
Software Design Considerations
427(1)
The Teja NP Software Platform
428(1)
The Teja C Programming Language
429(9)
Platform Support
438(3)
Conclusions
441(2)
References
442(1)
Index 443
Mark A. Franklin received his B.A., B.S.E.E. and M.S.E.E. from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently at Washington University in St. Louis where he has a joint appointment in Electrical Engineering and Computer Science, and holds the Urbauer Chair in Engineering. He founded and is Director of the Computer and Communications Research Center and until recently was the Director of the Undergraduate Program in Computer Engineering. Dr. Franklin is engaged in research, teaching and consulting in the areas of computer and communications architectures, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation. He is a Fellow of the IEEE, a member of the ACM, and has been an organizer and reviewer for numerous professional conferences including the HPCA8 Workshop on Network Processors (2002). He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chairman of the ACM SIGARCH (Special Interest Group on Computer Architecture). Patrick Crowley is an associate Professor in the Department of Computer Science & Engineering at Washington University in St. Louis, Missouri. His research interests are in computer and network systems architecture, with a current focus on the design of programmable embedded network systems and the invention of superior network monitoring and security techniques. He co-founded the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, and co-edited the three-book series, Network Processor Design. He serves as Associate Editor of the IEEE/ACM Transactions on Networking. In 2007, Crowley was chosen to join the DARPA Computer Science Study Group. Haldun Hadimioglu received his BS and MS degrees in Electrical Engineering at Middle East Technical University, Ankara Turkey and his Ph.D. in Computer Science from Polytechnic University in New York. He is currently an Industry Associate Professor in the Computer Science Department and a member of the Computer Engineering faculty at the Polytechnic University. He worked as a research engineer at PETAS, Ankara Turkey (1980-1982). Dr. Hadimioglu's research and teaching interests include Computer Architecture, Parallel and Distributed Systems, Networking and VLSI Design. He was a guest editor of the special issue on "Advances in High Performance Memory Systems," IEEE Transactions on Computers (Nov 2001) and has reviewed papers for leading journals such as the IEEE Transactions on Computers. Hadimioglu is a member of the IEEE, the ACM, and Sigma Xi. He has been an organizer of various workshops including, the ISCA Memory Wall (2000), ISCA Memory Performance Issues (2002, 2001) and HPCA8 Workshop on Network Processors (2002). He received Dedicated Faculty and Outstanding Faculty awards from Polytechnic students in 1995 and 1993, respectively. Peter Z. Onufryk received his B.S.E.E. from Rutgers University, M.S.E.E. from Purdue University, and Ph.D. in Electrical and Computer Engineering from Rutgers University. He is currently a director in the Internetworking Products Division at Integrated Device Technology, Inc. where he is responsible for architecture definition and validation of communications products. Before joining IDT, Peter was a researcher for thirteen years at AT&T Labs - Research (formally AT&T Bell Labs) where he worked on communications systems and parallel computer architectures. These included a number of parallel, cache-coherent multiprocessor and dataflow based machines that were targeted towards high performance military systems. Other work there focused on packet telephony and early network processors. Onufryk is a member of the IEEE. He was an organizer and program committee member of the HPCA8 Workshop on Network Processors 2002. Peter was the architect of four communications processors as well as numerous ASICs, boards, and systems.