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Reconfigurable Computing for High Performance Networking Applications |
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1 | (1) |
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Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform |
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2 | (1) |
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Reconfigurable Accelerators I |
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A Reconfigurable Audio Beamforming Multi-Core Processor |
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3 | (13) |
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A Regular Expression Matching Circuit Based on a Decomposed Automaton |
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16 | (13) |
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Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios |
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29 | (12) |
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Application Specific Memory Access, Reuse and Reordering for SDRAM |
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41 | (12) |
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Automatic Generation of FPGA-Specific Pipelined Accelerators |
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53 | (14) |
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HLS Tools for FPGA: Faster Development with Better Performance |
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67 | (12) |
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A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks |
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79 | (9) |
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A Compact Gaussian Random Number Generator for Small Word Lengths |
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88 | (6) |
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Accurate Floating Point Arithmetic through Hardware Error-Free Transformations |
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94 | (8) |
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Active Storage Networks for Accelerating K-Means Data Clustering |
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102 | (8) |
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An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems |
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110 | (8) |
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Mario-Alberto Ibarra-Manzano |
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CReAMS: An Embedded Multiprocessor Platform |
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118 | (7) |
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Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture |
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125 | (8) |
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Reconfigurable Processors |
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A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection |
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133 | (12) |
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Design, Implementation, and Verification of an Adaptable Processor in Lava HDL |
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145 | (12) |
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Towards an Adaptable Multiple-ISA Reconfigurable Processor |
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157 | (12) |
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FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments |
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169 | (12) |
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FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design |
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181 | (12) |
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Index to Constant Weight Codeword Converter |
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193 | (13) |
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On-Chip Ego-Motion Estimation Based on Optical Flow |
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206 | (12) |
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Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA |
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218 | (12) |
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Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction |
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230 | (12) |
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MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays |
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242 | (11) |
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FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA |
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253 | (8) |
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Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications |
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261 | (8) |
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Hierarchical Optical Flow Estimation Architecture Using Color Cues |
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269 | (6) |
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Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power |
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275 | (6) |
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Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers |
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281 | (6) |
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The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA |
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287 | (9) |
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A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology |
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296 | (6) |
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Reconfigurable Accelerators II |
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FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations |
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302 | (14) |
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FPGA Optimizations for a Pipelined Floating-Point Exponential Unit |
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316 | (12) |
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NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security |
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328 | (12) |
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Methodology and Simulation |
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A Correlation Power Analysis Attack against Tate Pairing on FPGA |
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340 | (10) |
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From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype |
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350 | (13) |
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Architectural Support for Multithreading on Reconfigurable Hardware |
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363 | (12) |
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High Performance Programmable FPGA Overlay for Digital Signal Processing |
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375 | (10) |
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Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture |
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385 | (12) |
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| Author Index |
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397 | |
