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Applied RC Design Methods and Tools |
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Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration |
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1 | (12) |
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Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration |
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13 | (13) |
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Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array |
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26 | (14) |
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Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture |
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40 | (13) |
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Table-Based Division by Small Integer Constants |
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53 | (11) |
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Heterogeneous Systems for Energy Efficient Scientific Computing |
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64 | (12) |
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The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms |
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76 | (13) |
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PPMC: A Programmable Pattern Based Memory Controller |
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89 | (13) |
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A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor |
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102 | (12) |
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Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration |
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114 | (12) |
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Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs |
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126 | (12) |
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ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs |
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138 | (13) |
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Shinya Takamaeda-Yamazaki |
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Scalable Memory Hierarchies for Embedded Manycore Systems |
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151 | (12) |
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Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays |
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163 | (11) |
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A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters |
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174 | (13) |
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Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations |
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187 | (15) |
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A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU |
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202 | (13) |
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Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration |
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215 | (12) |
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Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware |
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227 | (12) |
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A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem |
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239 | (12) |
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Optimising Performance of Quadrature Methods with Reduced Precision |
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251 | (13) |
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Critical Issues in Applied RC |
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Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform |
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264 | (12) |
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Securely Sealing Multi-FPGA Systems |
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276 | (14) |
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FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores |
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290 | (12) |
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High Performance Reconfigurable Architecture for Double Precision Floating Point Division |
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302 | (12) |
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A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems |
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314 | (6) |
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Constructing Cluster of Simple FPGA Boards for Cryptologic Computations |
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320 | (9) |
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Reconfigurable Multicore Architecture for Dynamic Processor Reallocation |
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329 | (6) |
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Efficient Communication for FPGA Clusters |
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335 | (7) |
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Performance Analysis of Reconfigurable Processors Using MVA Analysis |
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342 | (8) |
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PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs |
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350 | (7) |
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A Connection Router for the Dynamic Reconfiguration of FPGAs |
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357 | (8) |
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R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip |
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365 | (7) |
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Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms |
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372 | (7) |
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CRAIS: A Crossbar Based Adaptive Interconnection Scheme |
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379 | (6) |
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| Author Index |
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385 | |
