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E-book: Digital Design Using VHDL: A Systems Approach

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(University of British Columbia, Vancouver), , (Stanford University, California)
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  • Pub. Date: 17-Dec-2015
  • Publisher: Cambridge University Press
  • Language: eng
  • ISBN-13: 9781108232005
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Digital Design Using VHDL: A Systems ApproachLarger Image
  • Format: EPUB+DRM
  • Pub. Date: 17-Dec-2015
  • Publisher: Cambridge University Press
  • Language: eng
  • ISBN-13: 9781108232005
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This introductory textbook provides students with a system-level perspective and the tools they need to understand, analyze and design digital systems. Going beyond the design of simple combinational and sequential modules, it shows how such modules are used to build complete systems, reflecting real-world digital design. All the essential topics are covered, including design and analysis of combinational and sequential modules, as well as system timing and synchronization. It also teaches how to write VHDL-2008 HDL in a productive and maintainable style that enables CAD tools to do much of the tedious work. A complete introduction to digital design is given through clear explanations, extensive examples and online VHDL files. The teaching package is completed with lecture slides, labs and a solutions manual for instructors. Assuming no previous digital knowledge, this textbook is ideal for undergraduate digital design courses that will prepare students for modern digital practice.

Provides students with a system-level perspective and the tools they need to understand, analyze and design complete digital systems using VHDL. It goes beyond the design of simple combinational and sequential modules to show how such modules are used to build complete systems, reflecting digital design in the real world.

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Provides students with a system-level perspective and the tools they need to analyze and design complete digital systems using VHDL.
Preface xv
Acknowledgments xx
Part I Introduction
1 The digital abstraction
3(19)
1.1 Digital signals
3(2)
1.2 Digital signals tolerate noise
5(3)
1.3 Digital signals represent complex data
8(3)
1.3.1 Representing the day of the year
10(1)
1.3.2 Representing subtractive colors
11(1)
1.4 Digital logic functions
11(2)
1.5 VHDL description of digital circuits and systems
13(3)
1.6 Digital logic in systems
16(1)
Summary
17(1)
Bibliographic notes
18(1)
Exercises
18(4)
2 The practice of digital system design
22(21)
2.1 The design process
22(6)
2.1.1 Specification
22(2)
2.1.2 Concept development and feasibility
24(2)
2.1.3 Partitioning and detailed design
26(1)
2.1.4 Verification
27(1)
2.2 Digital systems are built from chips and boards
28(4)
2.3 Computer-aided design tools
32(2)
2.4 Moore's law and digital system evolution
34(2)
Summary
36(1)
Bibliographic notes
36(1)
Exercises
37(6)
Part II Combinational logic
3 Boolean algebra
43(15)
3.1 Axioms
43(1)
3.2 Properties
44(2)
3.3 Dual functions
46(1)
3.4 Normal form
47(1)
3.5 From equations to gates
48(3)
3.6 Boolean expressions in VHDL
51(3)
Summary
54(1)
Bibliographic notes
55(1)
Exercises
55(3)
4 CMOS logic circuits
58(24)
4.1 Switch logic
58(4)
4.2 Switch model of MOS transistors
62(6)
4.3 CMOS gate circuits
68(9)
4.3.1 Basic CMOS gate circuit
69(1)
4.3.2 Inverters, NANDs, and NORs
70(2)
4.3.3 Complex gates
72(3)
4.3.4 Tri-state circuits
75(1)
4.3.5 Circuits to avoid
76(1)
Summary
77(1)
Bibliographic notes
78(1)
Exercises
78(4)
5 Delay and power of CMOS circuits
82(23)
5.1 Delay of static CMOS gates
82(3)
5.2 Fan-out and driving large loads
85(1)
5.3 Fan-in and logical effort
86(3)
5.4 Delay calculation
89(3)
5.5 Optimizing delay
92(2)
5.6 Wire delay
94(4)
5.7 Power dissipation in CMOS circuits
98(3)
5.7.1 Dynamic power
98(1)
5.7.2 Static power
99(1)
5.7.3 Power scaling
100(1)
Summary
101(1)
Bibliographic notes
101(1)
Exercises
102(3)
6 Combinational logic design
105(24)
6.1 Combinational logic
105(1)
6.2 Closure
106(1)
6.3 Truth tables, minterms, and normal form
107(3)
6.4 Implicants and cubes
110(3)
6.5 Karnaugh maps
113(2)
6.6 Covering a function
115(1)
6.7 From a cover to gates
116(1)
6.8 Incompletely specified functions
117(2)
6.9 Product-of-sums implementation
119(2)
6.10 Hazards
121(2)
Summary
123(1)
Bibliographic notes
124(1)
Exercises
124(5)
7 VHDL descriptions of combinational logic
129(28)
7.1 The prime number circuit in VHDL
129(14)
7.1.1 A VHDL design entity
129(2)
7.1.2 The case statement
131(3)
7.1.3 The case? statement
134(2)
7.1.4 The if statement
136(1)
7.1.5 Concurrent signal assignment statements
136(1)
7.1.6 Selected signal assignment statements
137(1)
7.1.7 Conditional signal assignment statements
138(1)
7.1.8 Structural description
138(3)
7.1.9 The decimal prime number function
141(2)
7.2 A testbench for the prime number circuit
143(5)
7.3 Example: a seven-segment decoder
148(5)
Summary
153(1)
Bibliographic notes
154(1)
Exercises
154(3)
8 Combinational building blocks
157(42)
8.1 Multi-bit notation
157(1)
8.2 Decoders
157(6)
8.3 Multiplexers
163(8)
8.4 Encoders
171(2)
8.5 Arbiters and priority encoders
173(7)
8.6 Comparators
180(3)
8.7 Shifters
183(1)
8.8 Read-only memories
184(5)
8.9 Read—write memories
189(3)
8.10 Programmable logic arrays
192(1)
8.11 Data sheets
193(2)
8.12 Intellectual property
195(1)
Summary
195(1)
Bibliographic notes
196(1)
Exercises
196(3)
9 Combinational examples
199(22)
9.1 Multiple-of-3 circuit
199(2)
9.2 Tomorrow circuit
201(4)
9.3 Priority arbiter
205(2)
9.4 Tic-tac-toe
207(7)
Summary
214(1)
Exercises
215(6)
Part III Arithmetic circuits
10 Arithmetic circuits
221(29)
10.1 Binary numbers
221(3)
10.2 Binary addition
224(6)
10.3 Negative numbers and subtraction
230(7)
10.4 Multiplication
237(3)
10.5 Division
240(4)
Summary
244(1)
Exercises
245(5)
11 Fixed- and floating-point numbers
250(19)
11.1 Representation error: accuracy, precision, and resolution
250(2)
11.2 Fixed-point numbers
252(5)
11.2.1 Representation
252(3)
11.2.2 Operations
255(2)
11.3 Floating-point numbers
257(8)
11.3.1 Representation
257(1)
11.3.2 Denormalized numbers and gradual underflow
258(1)
11.3.3 Floating-point multiplication
259(1)
11.3.4 Floating-point addition/subtraction
260(5)
Summary
265(1)
Bibliographic note
265(1)
Exercises
265(4)
12 Fast arithmetic circuits
269(21)
12.1 Carry look-ahead
269(7)
12.2 Booth recoding
276(2)
12.3 Wallace trees
278(6)
12.4 Synthesis notes
284(2)
Summary
286(1)
Bibliographic notes
287(1)
Exercises
287(3)
13 Arithmetic examples
290(15)
13.1 Complex multiplication
290(1)
13.2 Converting between fixed- and floating-point formats
291(7)
13.2.1 Floating-point format
291(2)
13.2.2 Fixed- to floating-point conversion
293(4)
13.2.3 Floating- to fixed-point conversion
297(1)
13.3 FIR filter
298(2)
Summary
300(1)
Bibliographic note
300(1)
Exercises
300(5)
Part IV Synchronous sequential logic
14 Sequential logic
305(23)
14.1 Sequential circuits
305(2)
14.2 Synchronous sequential circuits
307(2)
14.3 Traffic-light controller
309(3)
14.4 State assignment
312(1)
14.5 Implementation of finite-state machines
313(3)
14.6 VHDL implementation of finite-state machines
316(8)
Summary
324(1)
Bibliographic notes
324(1)
Exercises
324(4)
15 Timing constraints
328(16)
15.1 Propagation and contamination delay
328(3)
15.2 The D flip-flop
331(1)
15.3 Setup- and hold-time constraints
331(3)
15.4 The effect of clock skew
334(2)
15.5 Timing examples
336(1)
15.6 Timing and logic synthesis
337(2)
Summary
339(1)
Bibliographic notes
340(1)
Exercises
340(4)
16 Datapath sequential logic
344(31)
16.1 Counters
344(8)
16.1.1 A simpler counter
344(2)
16.1.2 Up/down/load counter
346(3)
16.1.3 A timer
349(3)
16.2 Shift registers
352(4)
16.2.1 A simple shift register
352(1)
16.2.2 Left/right/load (LRL) shift register
353(1)
16.2.3 Universal shifter/counter
353(3)
16.3 Control and data partitioning
356(16)
16.3.1 Example: vending machine FSM
357(10)
16.3.2 Example: combination lock
367(5)
Summary
372(1)
Exercises
372(3)
17 Factoring finite-state machines
375(23)
17.1 A light flasher
375(7)
17.2 Traffic-light controller
382(11)
Summary
393(1)
Exercises
394(4)
18 Microcode
398(33)
18.1 Simple microcoded FSM
398(4)
18.2 Instruction sequencing
402(6)
18.3 Multi-way branches
408(2)
18.4 Multiple instruction types
410(4)
18.5 Microcode subroutines
414(6)
18.6 Simple computer
420(7)
Summary
427(1)
Bibliographic notes
427(1)
Exercises
428(3)
19 Sequential examples
431(22)
19.1 Divide-by-3 counter
431(1)
19.2 SOS detector
432(7)
19.3 Tic-tac-toe game
439(1)
19.4 Huffman encoder/decoder
439(9)
19.4.1 Huffman encoder
440(2)
19.4.2 Huffman decoder
442(6)
Summary
448(1)
Bibliographic note
448(1)
Exercises
448(5)
Part V Practical design
20 Verification and test
453(14)
20.1 Design verification
453(3)
20.1.1 Verification coverage
453(1)
20.1.2 Types of tests
454(1)
20.1.3 Static timing analysis
455(1)
20.1.4 Formal verification
455(1)
20.1.5 Bug tracking
456(1)
20.2 Test
456(5)
20.2.1 Fault models
456(1)
20.2.2 Combinational testing
457(1)
20.2.3 Testing redundant logic
457(1)
20.2.4 Scan
458(1)
20.2.5 Built-in self-test (BIST)
459(1)
20.2.6 Characterization
460(1)
Summary
461(1)
Bibliographic notes
462(1)
Exercises
462(5)
Part VI System design
21 System-level design
467(12)
21.1 System design process
467(1)
21.2 Specification
468(5)
21.2.1 Pong
468(3)
21.2.2 DES cracker
471(1)
21.2.3 Music player
472(1)
21.3 Partitioning
473(3)
21.3.1 Pong
474(1)
21.3.2 DES cracker
475(1)
21.3.3 Music synthesizer
475(1)
Summary
476(1)
Bibliographic notes
477(1)
Exercises
477(2)
22 Interface and system-level timing
479(18)
22.1 Interface timing
479(3)
22.1.1 Always valid timing
479(1)
22.1.2 Periodically valid signals
480(1)
22.1.3 Flow control
481(1)
22.2 Interface partitioning and selection
482(1)
22.3 Serial and packetized interfaces
483(3)
22.4 Isochronous timing
486(1)
22.5 Timing tables
487(2)
22.5.1 Event flow
488(1)
22.5.2 Pipelining and anticipatory timing
488(1)
22.6 Interface and timing examples
489(4)
22.6.1 Pong
489(1)
22.6.2 DES cracker
489(4)
22.6.3 Music player
493(1)
Summary
493(1)
Exercises
494(3)
23 Pipelines
497(24)
23.1 Basic pipelining
497(3)
23.2 Example pipelines
500(2)
23.3 Example: pipelining a ripple-carry adder
502(3)
23.4 Pipeline stalls
505(2)
23.5 Double buffering
507(4)
23.6 Load balance
511(1)
23.7 Variable loads
512(4)
23.8 Resource sharing
516(1)
Summary
517(1)
Bibliographic notes
518(1)
Exercises
518(3)
24 Interconnect
521(11)
24.1 Abstract interconnect
521(1)
24.2 Buses
522(2)
24.3 Crossbar switches
524(3)
24.4 Interconnection networks
527(2)
Summary
529(1)
Bibliographic notes
529(1)
Exercises
530(2)
25 Memory systems
532(19)
25.1 Memory primitives
532(4)
25.1.1 SRAM arrays
532(2)
25.1.2 DRAM chips
534(2)
25.2 Bit-slicing and banking memory
536(1)
25.3 Interleaved memory
537(3)
25.4 Caches
540(4)
Summary
544(1)
Bibliographic notes
545(1)
Exercises
545(6)
Part VII Asynchronous logic
26 Asynchronous sequential circuits
551(15)
26.1 Flow-table analysis
551(3)
26.2 Flow-table synthesis: the toggle circuit
554(4)
26.3 Races and state assignment
558(4)
Summary
562(1)
Bibliographic notes
563(1)
Exercises
563(3)
27 Flip-flops
566(14)
27.1 Inside a latch
566(2)
27.2 Inside a flip-flop
568(3)
27.3 CMOS latches and flip-flops
571(1)
27.4 Flow-table derivation of the latch
572(2)
27.5 Flow-table synthesis of a D flip-flop
574(2)
Summary
576(1)
Bibliographic notes
577(1)
Exercises
577(3)
28 Metastability and synchronization failure
580(12)
28.1 Synchronization failure
580(1)
28.2 Metastability
581(3)
28.3 Probability of entering and leaving an illegal state
584(1)
28.4 Demonstration of metastability
585(4)
Summary
589(1)
Bibliographic notes
590(1)
Exercises
590(2)
29 Synchronizer design
592(19)
29.1 Where are synchronizers used?
592(1)
29.2 Brute-force synchronizer
593(2)
29.3 The problem with multi-bit signals
595(1)
29.4 FIFO synchronizer
596(8)
Summary
604(1)
Bibliographic notes
605(1)
Exercises
605(6)
Part VIII Appendix: VHDL coding style and syntax guide
Appendix A VHDL coding style
611(11)
A.1 Basic principles
611(1)
A.2 All state should be in explicitly declared registers
612(2)
A.3 Define combinational design entities so that they are easy to read
614(1)
A.4 Assign all signals under all conditions
615(2)
A.5 Keep design entities small
617(1)
A.6 Large design entities should be structural
617(1)
A.7 Use descriptive signal names
618(1)
A.8 Use symbolic names for subfields of signals
618(1)
A.9 Define constants
618(1)
A.10 Comments should describe intention and give rationale, not state the obvious
619(1)
A.11 Never forget you are defining hardware
620(1)
A.12 Read and be a critic of VHDL code
620(2)
Appendix B VHDL syntax guide
622(31)
B.1 Comments, identifiers, and keywords
623(1)
B.2 Types
623(4)
B.2.1 Std_logic
624(1)
B.2.2 Boolean
624(1)
B.2.3 Integer
624(1)
B.2.4 Std_logic_vector
625(1)
B.2.5 Subtypes
625(1)
B.2.6 Enumeration
626(1)
B.2.7 Arrays and records
626(1)
B.2.8 Qualified expressions
627(1)
B.3 Libraries, packages, and using multiple files
627(1)
B.4 Design entities
628(1)
B.5 Slices, concatenation, aggregates, operators, and expressions
629(2)
B.6 Concurrent statements
631(5)
B.6.1 Concurrent signal assignment
632(2)
B.6.2 Component instantiation
634(2)
B.7 Multiple signal drivers and resolution functions
636(2)
B.8 Attributes
638(2)
B.9 Process statements
640(8)
B.9.1 The process sensitivity list and execution timing
641(3)
B.9.2 Wait and report statements
644(1)
B.9.3 If statements
644(1)
B.9.4 Case and matching case statements
644(2)
B.9.5 Signal and variable assignment statements
646(2)
B.10 Synthesizable process statements
648(5)
B.10.1 Type 1: purely combinational
649(1)
B.10.2 Type 2: edge-sensitive
649(1)
B.10.3 Type 3: edge-sensitive with asynchronous reset
650(3)
References 653(5)
Index of VHDL design entities 658(2)
Subject index 660
William J. Dally is the Willard R. and Inez Kerr Bell Professor of Engineering at Stanford University and Chief Scientist at NVIDIA Corporation. He and his group have developed system architecture, network architecture, signaling, routing and synchronization technology that can be found in most large parallel computers today. He is a Member of the National Academy of Engineering, a Fellow of the IEEE, a Fellow of the ACM and a Fellow of the American Academy of Arts and Sciences. He has received numerous honors including the ACM EckertMauchly Award, the IEEE Seymour Cray Award and the ACM Maurice Wilkes Award. R. Curtis Harting is a Software Engineer at Google and holds a PhD from Stanford University. He graduated with honors in 2007 from Duke University with a BSE, majoring in Electrical and Computer Engineering and Computer Science. He received his MS in 2009 from Stanford University. Tor M. Aamodt is an Associate Professor in the Department of Electrical and Computer Engineering at the University of British Columbia. Alongside his graduate students, he developed the GPGPU-Sim simulator. Three of his papers related to the architecture of general purpose GPUs have been selected as 'Top Picks' by IEEE Micro Magazine and one as a 'Research Highlight' by Communications of the ACM magazine. He was a Visiting Associate Professor in the Computer Science Department at Stanford University during his 20122013 sabbatical, and from 2004 to 2006 he worked at NVIDIA on the memory system architecture ('framebuffer') of the GeForce 8 Series GPU.
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