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E-book: Digital Integrated Circuit Design Using Verilog and Systemverilog

(Professor of Electrical and Computing Engineering at California State University, Northridge)
  • Format: EPUB+DRM
  • Pub. Date: 30-Sep-2014
  • Publisher: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • Language: eng
  • ISBN-13: 9780124095298
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  • Format: EPUB+DRM
  • Pub. Date: 30-Sep-2014
  • Publisher: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • Language: eng
  • ISBN-13: 9780124095298
Other books in subject:

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For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually work when turned into physical circuits. Throughout the book, many small examples are used to validate concepts and demonstrate how to apply design skills.This book takes readers who have already learned the fundamentals of digital design to the point where they can produce working circuits using modern design methodologies. It clearly explains what is useful for circuit design and what parts of the languages are only software, providing a non-theoretical, practical guide to robust, reliable and optimized hardware design and development.Produce working hardware: Covers not only syntax, but also provides design know-how, addressing problems such as synchronization and partitioning to produce working solutionsUsable examples: Numerous small examples throughout the book demonstrate concepts in an easy-to-grasp mannerEssential knowledge: Covers the vital design topics of synchronization, essential for producing working silicon; asynchronous interfacing techniques; and design techniques for circuit optimization, including partitioning

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Design robust, reliable and optimized digital integrated circuits using Verilog and SystemVerilog
About the author xi
Preface xiii
Acknowledgments xv
Chapter 1 Introduction
1(10)
Who should read this book
1(1)
Hardware description languages and methodology
2(1)
What this book covers
3(1)
Historical perspective
4(3)
Verilog and systemverilog
7(1)
Book organization
7(4)
Chapter 2 Bottom-up design
11(30)
Primitive instantiation
11(6)
Designing with primitives
17(4)
Identifiers and escaped identifiers
21(1)
Bus declarations
22(3)
Design hierarchy and test fixtures
25(8)
Port association
33(3)
Timescales
36(3)
Summary
39(2)
Chapter 3 Behavioral coding part I: blocks, variables, and operators
41(66)
Top-down design
42(1)
Synthesizable and nonsynthesizable code
43(1)
Register transfer level (RTL)
44(1)
Continuous assignments
45(2)
Implicit continuous assignments
47(1)
Functional blocks: always and initial
47(4)
Named blocks
51(1)
Sensitivity lists
52(2)
Splitting assignments
54(1)
Variables
54(23)
Nets
55(2)
Net aliases
57(1)
Net signal strength
58(1)
Registers
59(3)
Systemverilog variables
62(2)
Var variables
64(1)
Arrays
65(5)
Bidirectional buses
70(2)
Structures and unions
72(5)
Operators
77(27)
Assignment operators
77(5)
Equality operators
82(3)
Logical operators
85(2)
Bitwise operators
87(3)
Reduction operators
90(1)
Arithmetic operators
91(1)
Auto increment and auto decrement
92(2)
Relational operators
94(1)
Shift operators
94(5)
Concatenation operator
99(1)
Replication operator
99(2)
Conditional operator
101(1)
Systemverilog combined assignment operators
101(2)
Operator precedence
103(1)
Summary
104(3)
Chapter 4 Behavioral coding part II: defines, parameters, enumerated types, and packages
107(28)
Global definitions
107(6)
Parameters
113(2)
Overriding default values
115(3)
Local parameters
118(2)
Specify parameters
120(1)
Enumerated types
120(8)
Constants
128(1)
Packages
128(4)
Filling a scalable variable with all ones
132(1)
Summary
133(1)
Reference
134(1)
Chapter 5 Behavioral coding part III: loops and branches
135(36)
Loops
136(19)
While loop
136(3)
Do while loop
139(1)
For loop
140(4)
Foreach loop
144(1)
Forever loop
145(1)
Repeat loop
146(1)
Break and continue
147(1)
Disable
148(1)
Generate
148(3)
Multiway branching
151(1)
If statements
151(4)
Case statements
155(6)
Latch generation
161(3)
Unique and priority
164(4)
Summary
168(1)
Reference
169(2)
Chapter 6 Subroutines and interfaces
171(30)
Subroutines
172(1)
Tasks
172(9)
Functions
181(5)
Parameters in subroutines
186(1)
Managing subroutines
187(4)
Interfaces
191(4)
Interface modports
195(3)
Summary
198(3)
Chapter 7 Synchronization
201(48)
Latch instability
201(3)
Flipflops, latches, and violations
204(5)
Asynchronous assert, synchronous deassert
209(2)
Slow-speed single-bit clocked asynchronous interfaces
211(2)
High-speed single-bit clocked asynchronous interfaces
213(8)
Multiple high-speed single-bit clocked asynchronous interfaces
221(1)
Asynchronous parallel buses
222(18)
FIFO
224(11)
FIFO operation and throughput
235(3)
FIFO depth
238(2)
High-speed asynchronous serial links
240(7)
Summary
247(1)
References
247(2)
Chapter 8 Simulation, timing, and race conditions
249(12)
Simulation queues
249(2)
Race conditions
251(3)
Derived clocks and delta time
254(4)
Assertions
258(1)
Summary
259(1)
References
260(1)
Chapter 9 Architectural choices
261(32)
FPGA versus ASIC
261(3)
Design reuse
264(1)
Partitioning
265(5)
Area and speed optimization
270(11)
Power optimization
281(9)
Summary
290(1)
References
291(2)
Chapter 10 Design for testability
293(44)
Yield, testing, and defect level
294(6)
Fault modeling
300(4)
Activation and sensitization
304(1)
Logic scan
305(8)
Boundary scan
313(10)
Built in self-test
323(11)
Parametric testing
334(1)
Summary
334(1)
References
335(2)
Chapter 11 Library modeling
337(24)
Component libraries
337(2)
Cell models
339(7)
User-defined primitives
346(2)
Combinational cells
348(3)
Sequential cells
351(8)
Model performance
359(1)
Summary
359(1)
References
360(1)
Chapter 12 Design examples
361(28)
State machine
361(3)
FIR filters
364(12)
FIFO
376(6)
DMX receiver
382(7)
Appendix A SystemVerilog keywords 389(4)
Appendix B Standard combinational and sequential functions 393(12)
Appendix C Number systems 405(8)
Index 413
Ronald Mehler is a professor of electrical and computing engineering at California State University, Northridge. Before joining the faculty at CSUN, he worked in private industry for 20 years, mostly designing integrated circuits using hardware description languages and logic synthesis. The primary focus of his research has been on design automation for application specific integrated circuit (ASIC) development.