About the author |
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xi | |
Preface |
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xiii | |
Acknowledgments |
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xv | |
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1 | (10) |
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Who should read this book |
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1 | (1) |
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Hardware description languages and methodology |
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2 | (1) |
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3 | (1) |
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4 | (3) |
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Verilog and systemverilog |
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7 | (1) |
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7 | (4) |
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Chapter 2 Bottom-up design |
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11 | (30) |
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11 | (6) |
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Designing with primitives |
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17 | (4) |
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Identifiers and escaped identifiers |
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21 | (1) |
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22 | (3) |
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Design hierarchy and test fixtures |
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25 | (8) |
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33 | (3) |
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36 | (3) |
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39 | (2) |
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Chapter 3 Behavioral coding part I: blocks, variables, and operators |
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41 | (66) |
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42 | (1) |
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Synthesizable and nonsynthesizable code |
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43 | (1) |
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Register transfer level (RTL) |
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44 | (1) |
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45 | (2) |
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Implicit continuous assignments |
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47 | (1) |
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Functional blocks: always and initial |
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47 | (4) |
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51 | (1) |
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52 | (2) |
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54 | (1) |
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54 | (23) |
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55 | (2) |
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57 | (1) |
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58 | (1) |
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59 | (3) |
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62 | (2) |
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64 | (1) |
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65 | (5) |
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70 | (2) |
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72 | (5) |
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77 | (27) |
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77 | (5) |
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82 | (3) |
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85 | (2) |
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87 | (3) |
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90 | (1) |
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91 | (1) |
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Auto increment and auto decrement |
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92 | (2) |
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94 | (1) |
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94 | (5) |
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99 | (1) |
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99 | (2) |
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101 | (1) |
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Systemverilog combined assignment operators |
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101 | (2) |
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103 | (1) |
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104 | (3) |
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Chapter 4 Behavioral coding part II: defines, parameters, enumerated types, and packages |
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107 | (28) |
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107 | (6) |
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113 | (2) |
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Overriding default values |
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115 | (3) |
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118 | (2) |
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120 | (1) |
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120 | (8) |
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128 | (1) |
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128 | (4) |
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Filling a scalable variable with all ones |
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132 | (1) |
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133 | (1) |
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134 | (1) |
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Chapter 5 Behavioral coding part III: loops and branches |
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135 | (36) |
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136 | (19) |
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136 | (3) |
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139 | (1) |
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140 | (4) |
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144 | (1) |
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145 | (1) |
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146 | (1) |
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147 | (1) |
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148 | (1) |
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148 | (3) |
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151 | (1) |
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151 | (4) |
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155 | (6) |
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161 | (3) |
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164 | (4) |
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168 | (1) |
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169 | (2) |
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Chapter 6 Subroutines and interfaces |
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171 | (30) |
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172 | (1) |
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172 | (9) |
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181 | (5) |
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Parameters in subroutines |
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186 | (1) |
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187 | (4) |
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191 | (4) |
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195 | (3) |
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198 | (3) |
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Chapter 7 Synchronization |
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201 | (48) |
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201 | (3) |
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Flipflops, latches, and violations |
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204 | (5) |
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Asynchronous assert, synchronous deassert |
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209 | (2) |
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Slow-speed single-bit clocked asynchronous interfaces |
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211 | (2) |
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High-speed single-bit clocked asynchronous interfaces |
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213 | (8) |
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Multiple high-speed single-bit clocked asynchronous interfaces |
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221 | (1) |
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Asynchronous parallel buses |
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222 | (18) |
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224 | (11) |
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FIFO operation and throughput |
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235 | (3) |
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238 | (2) |
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High-speed asynchronous serial links |
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240 | (7) |
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247 | (1) |
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247 | (2) |
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Chapter 8 Simulation, timing, and race conditions |
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249 | (12) |
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249 | (2) |
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251 | (3) |
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Derived clocks and delta time |
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254 | (4) |
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258 | (1) |
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259 | (1) |
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260 | (1) |
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Chapter 9 Architectural choices |
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261 | (32) |
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261 | (3) |
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264 | (1) |
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265 | (5) |
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Area and speed optimization |
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270 | (11) |
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281 | (9) |
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290 | (1) |
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291 | (2) |
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Chapter 10 Design for testability |
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293 | (44) |
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Yield, testing, and defect level |
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294 | (6) |
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300 | (4) |
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Activation and sensitization |
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304 | (1) |
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305 | (8) |
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313 | (10) |
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323 | (11) |
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334 | (1) |
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334 | (1) |
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335 | (2) |
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Chapter 11 Library modeling |
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337 | (24) |
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337 | (2) |
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339 | (7) |
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346 | (2) |
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348 | (3) |
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351 | (8) |
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359 | (1) |
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359 | (1) |
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360 | (1) |
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Chapter 12 Design examples |
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361 | (28) |
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361 | (3) |
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364 | (12) |
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376 | (6) |
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382 | (7) |
Appendix A SystemVerilog keywords |
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389 | (4) |
Appendix B Standard combinational and sequential functions |
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393 | (12) |
Appendix C Number systems |
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405 | (8) |
Index |
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413 | |