This book covers all the main topics related to SSDs, from NAND Flash to memory controllers, from I/O interfaces (PCIe/SAS/SATA) to reliability, from errror correction codes (BCH and LDPC) to encryption, from Flash signal processing to hybrid storage.
The revised second edition of this respected text provides a state-of-the-art overview of the main topics relating to solid state drives (SSDs), covering NAND flash memories, memory controllers (including booth hardware and software), I/O interfaces (PCIe/SAS/SATA), reliability, error correction codes (BCH and LDPC), encryption, flash signal processing and hybrid storage.
Updated throughout to include all recent work in the field, significant changes for the new edition include:
- A new chapter on flash memory errors and data recovery procedures in SSDs for reliability and lifetime improvement
- Updated coverage of SSD Architecture and PCI Express Interfaces moving from PCIe Gen3 to PCIe Gen4 and including a section on NVMe over fabric (NVMf)
- An additional section on 3D flash memories
- An update on standard reliability procedures for SSDs
- Expanded coverage of BCH for SSDs, with a specific section on detection
- A new section on non-binary Low-Density Parity-Check (LDPC) codes, the most recent advancement in the field
- A description of randomization in the protection of SSD data against attacks, particularly relevant to 3D architectures
The SSD market is booming, with many industries placing a huge effort in this space, spending billions of dollars in R&D and product development. Moreover, flash manufacturers are now moving to 3D architectures, thus enabling an even higher level of storage capacity. This book takes the reader through the fundamentals and brings them up to speed with the most recent developments in the field, and is suitable for advanced students, researchers and engineers alike.
Dedication Page.- Preface.- Preface to the
2nd edition.- Foreword.- Acknowledgements.- About the editors.- 1. SSD
Architecture and PCI Express interface.- 2. SAS and SATA SSDs.- 3. Hybrid
Storage Systems.- 4. 2D NAND Flash technology.- 5. 3D NAND Flash memories
(new chapter).- 6. NAND Flash design.- 7. Solid State Drives: memory driven
design methodologies for optimal performance (new chapter).- 8. SSD
Reliability Assessment and Improvement.- 9. Reliability Issues in
Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation,
Recovery (new chapter).- 10. Efficient wear leveling in NAND Flash memory.
-11. BCH Codes for Solid-State-Drives.- 12. Low-Density Parity-Check (LDPC)
codes.-13. Protecting SSD data against attacks.- Index.
Dr. Rino Micheloni (rino.micheloni@ieee.org) is Vice-President and Fellow at Microsemi Corporation, where he currently runs the Flash Signal Processing Labs in Milan, Italy, with special focus on NAND Flash, Error Correction Codes, and Machine Learning. Prior to joining Microsemi, he was Fellow at PMC-Sierra, working on NAND Flash characterization, LDPC, and NAND Signal Processing as part of the team developing Flash controllers for PCIe SSDs. Before that, he was with IDT (Integrated Device Technology) as Lead Flash Technologist, driving the architecture and design of the BCH engine in the worlds first PCIe NVMe SSD controller. Early in his career, he led NAND design teams at STMicroelectronics, Hynix, and Infineon/Qimonda; during this time, he developed the industrys first MLC NOR device with embedded ECC technology and the industrys first MLC NAND with embedded BCH.
Dr. Micheloni is IEEE Senior Member, he has co-authored more than 70 publications, andhe holds 278 patents worldwide (including 131 US patents). He received the STMicroelectronics Exceptional Patent Award in 2003 and 2004, and the Infineon/Qimonda IP Award in 2007.
Dr. Micheloni has published the following books with Springer: Solid-State-Drives (SSDs) Modeling (2017), 3D Flash Memories (2016), Inside Solid State Drives (2013), Inside NAND Flash Memories (2010), Error Correction Codes for Non-Volatile Memories (2008), Memories in Wireless Systems (2008), and VLSI-Design of Non-Volatile Memories (2005).
Alessia Marelli is technical leader at Microsemi Corporation, where she takes care of the Error Correction Code and Machine Learning algorithms. She joined Microsemi from PMC-Sierra where she was part of the NAND characterization team as senior engineer with a special focus on Data Analysis and Flash Management algorithms. Before that, she was with IDT as senior designer working on ECC solutions for Flashcontrollers. Prior IDT, she worked in Qimonda/Infineon as digital designer and in STMicroelectronics defining the Error Correction Code for the industrys first MLC NAND with embedded BCH. She received her degree in Mathematical Science from Università degli Studi di Milano Bicocca, Italy in 2003 with a thesis about ECC applied to Flash Memories.
Alessia holds more than 20 patents regarding Error Correction Codes and is co-author of Inside Solid State Drives (Springer, 2013), Inside NAND Flash Memories (Springer, 2010), and Error Correction Codes for Non-Volatile Memories (Springer, 2008).
Kam Eshghi is Vice President of Strategy & Business Development at Lightbits Labs, a stealth-mode start-up developing innovative storage technologies for cloud infrastructure. Kam joined Lightbits Labs from DellEMC, where he was Vice President of Strategic Alliances for the DSSD division. Kam developed and managed startup DSSD's strategic partnership with EMC, ultimately leading to EMCs acquisition of DSSD.
Previously, as Sr. Director of Marketing & Business Development at Integrated Device Technology (IDT) Kam build IDTs NVMe Controller business from startup to industry leader. That business was then sold to PMC and is today a successful product line at Microsemi. Earlier in his career, Kam helped build product lines in storage, compute and networking markets at HP, Intel, Crosslayer Networks, and Synopsys.
Kam has a M.S. in Electrical Engineering & Computer Science and a Master of Business Administration, from Massachusetts Institute of Technology and U.C. Berkeley, respectively.
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