Update cookies preferences

E-book: Networks-on-Chip: From Implementations to Programming Paradigms

(Assistant Professor of the College of Computer, NUDT), (Lecturer of the College of Computer, NUDT), Editor-in-chief (Professor, Vice Dean ), (Assistant Professor of the College of Computer, NUDT), (Assistant Professor of the College of Computer, NUDT)
  • Format: EPUB+DRM
  • Pub. Date: 04-Dec-2014
  • Publisher: Morgan Kaufmann Publishers In
  • Language: eng
  • ISBN-13: 9780128011782
Other books in subject:
  • Format - EPUB+DRM
  • Price: 54,59 €*
  • * the price is final i.e. no additional discount will apply
  • Add to basket
  • Add to Wishlist
  • This ebook is for personal use only. E-Books are non-refundable.
Networks-on-Chip: From Implementations to Programming ParadigmsLarger Image
  • Format: EPUB+DRM
  • Pub. Date: 04-Dec-2014
  • Publisher: Morgan Kaufmann Publishers In
  • Language: eng
  • ISBN-13: 9780128011782
Other books in subject:

DRM restrictions

  • Copying (copy/paste):

    not allowed

  • Printing:

    not allowed

  • Usage:

    Digital Rights Management (DRM)
    The publisher has supplied this book in encrypted form, which means that you need to install free software in order to unlock and read it.  To read this e-book you have to create Adobe ID More info here. Ebook can be read and downloaded up to 6 devices (single user with the same Adobe ID).

    Required software
    To read this ebook on a mobile device (phone or tablet) you'll need to install this free app: PocketBook Reader (iOS / Android)

    To download and read this eBook on a PC or Mac you need Adobe Digital Editions (This is a free app specially developed for eBooks. It's not the same as Adobe Reader, which you probably already have on your computer.)

    You can't read this ebook with Amazon Kindle

Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms.

This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.

  • Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.
  • The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space
  • Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics.
  • Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.

More info

Provides a thorough and bottom-up exploration of NoC design
Preface xv
About the Editor-in-Chief and Authors xix
Part I Prologue
Chapter 1 Introduction
3(50)
1.1 The Dawn of the Many-Core Era
3(2)
1.2 Communication-Centric Cross-Layer Optimizations
5(2)
1.3 A Baseline Design Space Exploration of NoCs
7(10)
1.3.1 Topology
8(1)
1.3.2 Routing Algorithm
9(2)
1.3.3 Flow Control
11(2)
1.3.4 Router Microarchitecture
13(3)
1.3.5 Performance Metric
16(1)
1.4 Review of NoC Research
17(6)
1.4.1 Research on Topologies.
17(1)
1.4.2 Research on Unicast Routing
18(1)
1.4.3 Research on Supporting Collective Communications
19(1)
1.4.4 Research on Flow Control
20(2)
1.4.5 Research on Router Microarchitecture
22(1)
1.5 Trends of Real Processors
23(15)
1.5.1 The MIT Raw Processor
23(1)
1.5.2 The Tilera TILE64 Processor
24(2)
1.5.3 The Sony/Toshiba/IBM Cell Processor
26(2)
1.5.4 The U.T. Austin TRIPS Processor
28(1)
1.5.5 The Intel Teraflops Processor
29(1)
1.5.6 The Intel SCC Processor
30(2)
1.5.7 The Intel Larrabee Processor
32(2)
1.5.8 The Intel Knights Corner Processor
34(2)
1.5.9 Summary of Real Processors
36(2)
1.6 Overview of the Book
38(2)
References
40(13)
Part II Logic Implementations
Chapter 2 A Single-Cycle Router with Wing Channels
53(24)
2.1 Introduction
53(2)
2.2 The Router Architecture
55(7)
2.2.1 The Overall Architecture
56(4)
2.2.2 Wing Channels
60(2)
2.3 Microarchitecture Designs
62(5)
2.3.1 Channel Dispensers
62(2)
2.3.2 Fast Arbiter Components
64(1)
2.3.3 SIG Managers and SIG Controllers
65(2)
2.4 Experimental Results
67(7)
2.4.1 Simulation Infrastructures
67(1)
2.4.2 Pipeline Delay Analysis
67(1)
2.4.3 Latency and Throughput
68(5)
2.4.4 Area and Power Consumption
73(1)
2.5
Chapter Summary
74(1)
References
74(3)
Chapter 3 Dynamic Virtual Channel Routers with Congestion Awareness
77(30)
3.1 Introduction
77(2)
3.2 DVC with Congestion Awareness
79(3)
3.2.1 DVC Scheme
79(2)
3.2.2 Congestion Avoidance Scheme
81(1)
3.3 Multiple-Port Shared Buffer with Congestion Awareness
82(3)
3.3.1 DVC Scheme Among Multiple Ports
82(2)
3.3.2 Congestion Avoidance Scheme
84(1)
3.4 DVC Router Microarchitecture
85(6)
3.4.1 VC Control Module
86(2)
3.4.2 Metric Aggregation and Congestion Avoidance
88(2)
3.4.3 VC Allocation Module
90(1)
3.5 HiBB Router Microarchitecture
91(5)
3.5.1 VC Control Module
92(1)
3.5.2 VC Allocation and Output Port Allocation
92(3)
3.5.3 VC Regulation
95(1)
3.6 Evaluation
96(6)
3.6.1 DVC Router Evaluation
96(2)
3.6.2 HiBB Router Evaluation
98(4)
3.7
Chapter Summary
102(1)
References
102(5)
Chapter 4 Virtual Bus Structure-Based Network-on-Chip Topologies
107(34)
4.1 Introduction
108(1)
4.2 Background
109(1)
4.3 Motivation
110(4)
4.3.1 Baseline On-Chip Communication Networks
110(1)
4.3.2 Analysis of NoC Problems
111(2)
4.3.3 Advantages of a Transaction-Based Bus
113(1)
4.4 The VBON
114(11)
4.4.1 Interconnect Structures
114(2)
4.4.2 The VB Mechanism
116(7)
4.4.3 Starvation and Deadlock Avoidance
123(1)
4.4.4 The VBON Router Microarchitecture
124(1)
4.5 Evaluation
125(10)
4.5.1 Simulation Infrastructures
126(3)
4.5.2 Synthetic Traffic Evaluations
129(3)
4.5.3 Real Application Evaluations
132(1)
4.5.4 Power Consumption Analysis
132(1)
4.5.5 Overhead Analysis
132(3)
4.6
Chapter Summary
135(1)
References
136(5)
Part III Routing And Flow Control
Chapter 5 Routing Algorithms for Workload Consolidation
141(34)
5.1 Introduction
142(1)
5.2 Background
143(2)
5.3 Motivation
145(3)
5.3.1 Insufficient Information
145(1)
5.3.2 Intraregion Interference
145(2)
5.3.3 Inter-Region Interference
147(1)
5.4 Destination-Based Adaptive Routing
148(7)
5.4.1 Destination-Based Selection Strategy
148(4)
5.4.2 Routing Function Design
152(3)
5.5 Evaluation
155(12)
5.5.1 Evaluation of Routing Functions
156(2)
5.5.2 Single-Region Performance
158(3)
5.5.3 Multiple-Region Performance
161(2)
5.5.4 CMesh Evaluation
163(3)
5.5.5 Hardware Overhead
166(1)
5.6 Analysis and Discussion
167(2)
5.6.1 In-Depth Analysis of Interference
167(2)
5.6.2 Design Space Exploration
169(1)
5.7
Chapter Summary
169(1)
References
170(5)
Chapter 6 Flow Control for Fully Adaptive Routing
175(40)
6.1 Introduction
176(3)
6.2 Background
179(1)
6.2.1 Deadlock Avoidance Theories
179(1)
6.2.2 Fully Adaptive Routing Algorithms
179(1)
6.3 Motivation
180(1)
6.3.1 VC Reallocation
180(1)
6.3.2 Routing Flexibility
180(1)
6.4 Flow Control and Routing Designs
181(9)
6.4.1 Whole Packet Forwarding
182(3)
6.4.2 Aggressive VC Reallocation for EVCs
185(3)
6.4.3 Maintain Routing Flexibility
188(1)
6.4.4 Router Microarchitecture
188(2)
6.5 Evaluation on Synthetic Traffic
190(9)
6.5.1 Performance of Synthetic Workloads
191(1)
6.5.2 Buffer Utilization of Routing Algorithms
192(2)
6.5.3 Sensitivity to Network Design
194(5)
6.6 Evaluation of PARSEC Workloads
199(2)
6.6.1 Methodology and Configuration
199(1)
6.6.2 Performance
200(1)
6.7 Detailed Analysis of Flow Control
201(6)
6.7.1 The Detailed Buffer Utilization
201(3)
6.7.2 The Effect of Flow Control on Fairness
204(3)
6.8 Further Discussion
207(2)
6.8.1 Packet Length
207(1)
6.8.2 Dynamically Allocated Multiqueue and Hybrid Flow Controls
208(1)
6.9
Chapter Summary
209(1)
Appendix: Logical Equivalence of Alg and Alg + WPF
209(2)
References
211(4)
Chapter 7 Deadlock-Free Flow Control for Torus Networks-on-Chip
215(40)
7.1 Introduction
216(2)
7.2 Limitations of Existing Designs
218(3)
7.2.1 Dateline
218(1)
7.2.2 Localized Bubble Scheme
219(1)
7.2.3 Critical Bubble Scheme
219(1)
7.2.4 Inefficiency with Variable-Size Packets
220(1)
7.3 Flit Bubble Flow Control
221(4)
7.3.1 Theoretical Description
221(1)
7.3.2 FBFC-Localized
222(1)
7.3.3 FBFC-Critical
223(1)
7.3.4 Starvation
224(1)
7.4 Router Microarchitecture
225(2)
7.4.1 FBFC Routers
225(1)
7.4.2 VCT Routers
226(1)
7.5 Methodology
227(1)
7.6 Evaluation on 1D Tori (Rings)
228(3)
7.6.1 Performance
228(2)
7.6.2 Buffer Utilization
230(1)
7.6.3 Latency of Short and Long Packets
231(1)
7.7 Evaluation on 2D Tori
231(9)
7.7.1 Performance fora 4 x 4 Torus
231(2)
7.7.2 Sensitivity to SFP Ratios
233(1)
7.7.3 Sensitivity to Buffer Size
234(2)
7.7.4 Scalability for an 8 x 8 Torus
236(1)
7.7.5 Effect of Starvation
236(2)
7.7.6 Real Application Performance
238(1)
7.7.7 Large-Scale Systems and Message Passing
239(1)
7.8 Overheads: Power and Area
240(8)
7.8.1 Methodology
240(1)
7.8.2 Power Efficiency
241(3)
7.8.3 Area
244(1)
7.8.4 Comparison with Meshes
245(3)
7.9 Discussion and Related Work
248(1)
7.9.1 Discussion
248(1)
7.9.2 Related Work
248(1)
7.10
Chapter Summary
249(1)
References
249(6)
Part IV Programming Paradigms
Chapter 8 Supporting Cache-Coherent Collective Communications
255(30)
8.1 Introduction
256(2)
8.2 Message Combination Framework
258(5)
8.2.1 MCT Format
260(1)
8.2.2 Message Combination Example
260(3)
8.2.3 Insufficient MCT Entries
263(1)
8.3 BAM Routing
263(2)
8.4 Router Pipeline and Microarchitecture
265(2)
8.5 Evaluation
267(11)
8.5.1 Performance
269(3)
8.5.2 Comparing Multicast VN Configurations
272(2)
8.5.3 MCT Size
274(2)
8.5.4 Sensitivity to Network Design
276(2)
8.6 Power Analysis
278(2)
8.7 Related Work
280(1)
8.7.1 Message Combination
280(1)
8.7.2 NoC Multicast Routing
280(1)
8.8
Chapter Summary
281(1)
References
281(4)
Chapter 9 Network-on-Chip Customizations for Message Passing Interface Primitives
285(32)
9.1 Introduction
286(1)
9.2 Background
287(2)
9.3 Motivation
289(1)
9.3.1 MPI Adaption in NoC Designs
289(1)
9.3.2 Optimizations of MPI Functions
290(1)
9.4 Communication Customization Architectures
290(12)
9.4.1 Architecture Overview
290(2)
9.4.2 The Customized NoC Design: VBON
292(1)
9.4.3 The MPI Primitive Implementation: MU
292(10)
9.5 Evaluation
302(10)
9.5.1 Methodology
302(1)
9.5.2 Experimental Results
303(9)
9.6
Chapter Summary
312(1)
References
312(5)
Chapter 10 Message Passing Interface Communication Protocol Optimizations
317(36)
10.1 Introduction
318(1)
10.2 Background
319(7)
10.2.1 Communication Protocols in MPI
319(1)
10.2.2 Existing Problems
320(5)
10.2.3 Related Work
325(1)
10.3 Motivation
326(2)
10.4 Adaptive Communication Mechanisms
328(10)
10.4.1 Goals and Approaches
328(1)
10.4.2 Baseline MPI-Accelerated NoC Designs
329(2)
10.4.3 ADCM Architectural Support
331(6)
10.4.4 Comparison with the Ideal Protocol
337(1)
10.5 Evaluation
338(9)
10.5.1 Methodology
338(2)
10.5.2 Synthetic Traffic Results
340(3)
10.5.3 Real Application Results
343(3)
10.5.4 Sensitivity Analysis
346(1)
10.5.5 The Hardware Overhead
346(1)
10.6
Chapter Summary
347(1)
References
348(5)
Part V Epilogue
Chapter 11 Conclusions and Future Work
353(4)
11.1 Conclusions
353(2)
11.2 Future Work
355(2)
Index 357
Sheng Ma received the B.S. and Ph.D. degrees in computer science and technology from the National University of Defense Technology (NUDT) in 2007 and 2012, respectively. He visited the University of Toronto from Sept. 2010 to Sept. 2012. He is currently an Assistant Professor of the College of Computer, NUDT. His research interests include on-chip networks, SIMD architectures and arithmetic unit designs. Libo Huang received the B.S. and Ph.D. degree in computer engineering from National University of Defense Technology, PR China, in 2005 and 2010 respectively. From 2010, he was a Lecturer with the Department of Computer Science. His research interests include computer architecture, hardware/software Codesign, VLSI design, on-chip communication. He served as the technical reviewer of several conference and journals, e.g. MEJ, IJHPSA, ICCE 2010. Since 2004, he authored more than 20 papers in internationally recognized journals and conferences Mingche Lai received the PhD degree in computer engineering from NUDT in 2008. Currently, he is an Associate Professor with College of Computer, NUDT, and employed to develop high-performance computer interconnection systems. Since 2008, he has also been a Faculty Member with National Key Laboratory for Parallel and Distributed Processing of China. His research interests include on-chip networks, optical communication, many-core processor architecture, hardware/software co-design. He is a member of the IEEE and ACM Wei Shi received the PhD degree in computer Science from the National University of Defense Technology (NUDT) in 2010. Currently, he is an Assistant Professor of the College of Computer, NUDT, and employed to develop high-performance processors. His research interests include computer architecture, VLSI design, on-chip communication and asynchronous circuit techniques Zhiying Wang received the PhD degree in electrical engineering from the National University of Defense Technology in 1988. He is currently a professor with College of Computer, NUDT. He has contributed over 10 invited chapters to book volumes, published 240 papers in archival journals and refereed conference proceedings, and delivered over 30 keynotes. His main research fields include computer architecture, computer security, VLSI design, reliable architecture, multicore memory system and asynchronous circuit. He is a member of the IEEE and ACM.
More information about ebooks More information about ebooks
Permanent link: https://www.kriso.ee/db/97801280117826e.html
Keywords: