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1 Why Optoelectronic Circuits in Nanometer CMOS? |
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1 | (12) |
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1.1 Long-Haul Communication |
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2 | (1) |
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1.2 Fiber to the Home (FTTH) |
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3 | (1) |
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4 | (1) |
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1.4 Optical Interconnects |
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5 | (2) |
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7 | (3) |
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10 | (3) |
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11 | (2) |
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2 Optical Communications Fundamentals |
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13 | (24) |
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2.1 Optical Communication Building Blocks |
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13 | (5) |
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2.1.1 Optical Transmitter |
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13 | (1) |
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14 | (1) |
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15 | (3) |
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18 | (2) |
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2.2.1 Binary Data Formats |
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18 | (1) |
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2.2.2 Multilevel Signaling |
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19 | (1) |
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20 | (1) |
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21 | (1) |
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21 | (3) |
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24 | (2) |
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26 | (2) |
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2.8 Bandwidth and Rise/Fall Times |
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28 | (1) |
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2.9 Intersymbol Interference (ISI) |
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29 | (1) |
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30 | (1) |
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31 | (2) |
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33 | (1) |
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33 | (4) |
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34 | (3) |
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37 | (22) |
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3.1 Optical Absorption and Photocurrent Generation |
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37 | (2) |
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3.2 Carrier Drift and Diffusion |
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39 | (6) |
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40 | (2) |
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42 | (3) |
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3.3 Photodiode Capacitance |
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45 | (1) |
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46 | (1) |
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47 | (5) |
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3.5.1 Internal Quantum Efficiency |
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48 | (1) |
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3.5.2 Optical Quantum Efficiency |
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48 | (4) |
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3.6 Photodiode Responsivity |
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52 | (2) |
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3.7 Photodiode Dark and Noise Currents |
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54 | (1) |
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3.8 Photodiode Small-Signal and Noise Equivalent Circuit Model |
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55 | (4) |
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57 | (2) |
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59 | (8) |
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4.1 Discrete Photodiodes for Visible Light |
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59 | (2) |
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4.2 Discrete Photodiodes for Infrared Light |
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61 | (2) |
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4.3 External Photodetector Connected with Bond Wires |
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63 | (1) |
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4.4 External Photodetector Connected Using Flip-Chip Technique |
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63 | (4) |
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65 | (2) |
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5 Integrated Photodiodes in Nanometer CMOS Technologies |
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67 | (38) |
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5.1 Effects of Technology Selection and Scaling on Photodiode Performance |
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67 | (2) |
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5.2 Classical PN Junctions |
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69 | (10) |
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5.3 Double-Junction Photodiodes |
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79 | (12) |
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5.3.1 PW/DNW/P-Substrate Double Photodiode |
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79 | (4) |
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5.3.2 P+/NW/P-Sub Avalanche Double Photodiode |
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83 | (6) |
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5.3.3 P+/NW/P-Substrate Photodiode with Guard |
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89 | (2) |
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91 | (2) |
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93 | (3) |
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5.6 Spatially Modulated Light Detector |
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96 | (2) |
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5.7 Triple Junction Photodetector |
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98 | (1) |
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5.8 Avalanche Photodiodes |
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99 | (2) |
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5.9 Comparison of Photodiodes |
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101 | (4) |
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103 | (2) |
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6 Transimpedance Amplifiers |
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105 | (58) |
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6.1 Transimpedance Gain, Bandwidth, and Noise |
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105 | (1) |
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6.2 Effect of Technology Scaling |
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106 | (1) |
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6.3 Simplest Preamplifier |
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107 | (1) |
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108 | (19) |
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6.4.1 Common Gate Input Stage |
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109 | (8) |
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6.4.2 Regulated-Cascode TIA |
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117 | (5) |
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6.4.3 Inverter Based Common-Drain Feedback TIA |
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122 | (5) |
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6.5 Shunt-Shunt Feedback TIA |
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127 | (21) |
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129 | (2) |
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6.5.2 Noise Analysis of Shunt Feedback TIA |
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131 | (1) |
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132 | (1) |
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6.5.4 TIA with Common-Source Input Stage |
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133 | (1) |
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6.5.5 Multistage Inverter Based CMOS TIA |
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134 | (6) |
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6.5.6 Noise Canceling TIA |
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140 | (5) |
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6.5.7 Inverter Based Cascode TIA |
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145 | (3) |
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148 | (1) |
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6.7 TIA with Gain Control |
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149 | (1) |
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6.8 TIA with Gain Compression |
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150 | (3) |
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6.9 Bandwidth Enhancement Techniques for TIAs |
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153 | (10) |
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153 | (2) |
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155 | (2) |
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6.9.3 Active Inductive Peaking |
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157 | (1) |
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6.9.4 Negative Capacitance |
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158 | (1) |
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159 | (4) |
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163 | (20) |
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164 | (1) |
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165 | (1) |
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165 | (1) |
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7.4 Continuous Time Linear Equalizer (CTLE) with Multi-Shunt-Shunt Feedbacks |
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166 | (1) |
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7.5 Inductive Load Equalizer |
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167 | (2) |
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7.6 Adaptive Equalization |
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169 | (3) |
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7.6.1 Continuous Time Adaptive Equalizer |
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169 | (2) |
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7.6.2 Discrete Time Adaptive Equalizer |
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171 | (1) |
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7.7 Continuous Time FIR Filter Implementation |
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172 | (3) |
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7.8 Discrete Time FIR Filter Implementation |
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175 | (1) |
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7.9 Nonlinear Equalization |
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176 | (7) |
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7.9.1 Decision Feedback Equalizer (DFE) |
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177 | (2) |
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7.9.2 Maximum Likelihood Sequence Estimator (MLSE) |
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179 | (2) |
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181 | (2) |
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183 | (16) |
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183 | (1) |
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184 | (1) |
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185 | (1) |
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8.4 Differential Post Amplifier |
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186 | (1) |
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8.5 Amplifier with Automatic Gain Control |
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187 | (3) |
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190 | (1) |
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191 | (2) |
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8.8 Broad Band Amplifier Techniques |
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193 | (6) |
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8.8.1 Cherry-Hooper Amplifiers |
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194 | (1) |
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8.8.2 Interleaved Active Feedback |
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195 | (1) |
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196 | (1) |
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197 | (2) |
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9 Laser and Modulator Drivers |
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199 | (18) |
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9.1 LEDs, Laser Diodes, and VCSELs |
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199 | (3) |
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201 | (1) |
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9.2 Laser and Modulator Driver |
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202 | (1) |
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9.3 Laser Driver Specifications |
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203 | (3) |
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9.3.1 Rise and Fall Times |
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203 | (1) |
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203 | (1) |
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204 | (1) |
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9.3.4 Turn-on Delay (ToD) |
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205 | (1) |
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9.3.5 Output Voltage (Compliance Voltage) |
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206 | (1) |
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9.4 Laser Driver Circuit Design |
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206 | (7) |
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206 | (1) |
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206 | (2) |
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9.4.3 High Voltage Laser Driver |
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208 | (5) |
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9.5 Laser Automatic Power Control |
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213 | (1) |
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214 | (3) |
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214 | (1) |
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9.6.2 Modulator Driver Circuitry |
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215 | (1) |
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216 | (1) |
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10 Optoelectronic Circuits in Nanometer CMOS Technology |
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217 | (24) |
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10.1 Fully Integrated Optical Receivers |
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217 | (8) |
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10.1.1 180 nm CMOS Fully Integrated Optical Receiver |
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218 | (2) |
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10.1.2 65 nm CMOS Fully Integrated Optical Receiver |
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220 | (1) |
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10.1.3 40 nm CMOS Fully Integrated Optical Receiver |
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221 | (4) |
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10.2 Infrared Optical Receivers with External Photodiode |
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225 | (9) |
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10.2.1 Infrared Optical Receiver in 90 nm CMOS with External Photodiode |
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225 | (5) |
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10.2.2 Infrared Optical Receivers in 40 nm CMOS with External Photodiode |
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230 | (4) |
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234 | (7) |
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234 | (1) |
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235 | (3) |
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238 | (1) |
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239 | (2) |
Index |
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241 | |