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E-book: Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture

(Ryerson University, Toronto, Ontario, Canada)
  • Format: 346 pages
  • Pub. Date: 19-Dec-2017
  • Publisher: CRC Press Inc
  • Language: eng
  • ISBN-13: 9781482282245
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Reconfigurable Computing Systems Engineering: Virtualization of Computing ArchitectureLarger Image
  • Format: 346 pages
  • Pub. Date: 19-Dec-2017
  • Publisher: CRC Press Inc
  • Language: eng
  • ISBN-13: 9781482282245
Other books in subject:

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Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture describes the organization of reconfigurable computing system (RCS) architecture and discusses the pros and cons of different RCS architecture implementations. Providing a solid understanding of RCS technology and where its most effective, this book:











Details the architecture organization of RCS platforms for application-specific workloads Covers the process of the architectural synthesis of hardware components for system-on-chip (SoC) for the RCS Explores the virtualization of RCS architecture from the system and on-chip levels Presents methodologies for RCS architecture run-time integration according to mode of operation and rapid adaptation to changes of multi-parametric constraints Includes illustrative examples, case studies, homework problems, and references to important literature

A solutions manual is available with qualifying course adoption.

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture offers a complete road map to the synthesis of RCS architecture, exposing hardware design engineers, system architects, and students specializing in designing FPGA-based embedded systems to novel concepts in RCS architecture organization and virtualization.

Reviews

"Other texts having a similar focus tend to become entangled in technical details relating to a particular programming language, set of computer aided design tools, or device technology. As a result, these texts usually have a relatively short shelf life before they become obsolete. This text, on the other hand, is unique in that it stays within the realm of concepts and top-level design analysis and methodology, allowing it to be, and remain, applicable and relevant over a wide range of technologies." Dr. Jason D. Bakos, University of South Carolina, Columbia, USA

"The systematic representation of material, the detailed discussion of the main concepts, and the analysis of pros/cons of different approaches in architecture virtualization and static and dynamic integration will make this book very useful for engineers and students specializing in the development and design of field-programmable gate array (FPGA)-based reconfigurable computing systems." From the Foreword by Dr. Karen Safaryan, Vice President and Chief Technology Officer, Unique Broadband Systems, Ltd. and Director of R&D and Engineering, UBS-Axcera, Inc. Canada

Foreword xiii
Preface xv
Acknowledgments xix
Author xxi
List of Abbreviations xxiii
1 Introduction to Reconfigurable Computing Systems 1(24)
1.1 Introduction
1(3)
1.2 Computational Process and Classification of Computing Architectures
4(3)
1.3 Formal Definition of Computing Architecture
7(1)
1.4 Correspondence between the Task and the Computing Architecture
8(1)
1.5 Concept of a Computing System with a Programmable Procedure
9(4)
1.6 Concept of an Application-Specific Computing System
13(3)
1.7 Concept of the Computing System with Programmable Architecture
16(1)
1.8 Organization of RCS and Major Components of the RCS Architecture
17(3)
1.9 Summary
20(2)
Exercises and Problems
22(1)
References
23(2)
2 Organization of the Field of Configurable Resources 25(46)
2.1 Introduction
25(1)
2.2 Granularity of Logic Elements for the FCR
26(5)
2.2.1 Granularity of Basic Logic Elements versus Complexity of Connectivity
26(2)
2.2.2 Granularity of Basic Logic Elements for the FCR
28(3)
2.3 Heterogeneous Organization of the FCR
31(7)
2.3.1 General Organization of the Heterogeneous FCR
31(2)
2.3.2 Multilevel Organization of Heterogeneous FCR
33(2)
2.3.3 Effectiveness of Resource Utilization in Heterogeneous FCR
35(3)
2.4 Dynamic versus Static Reconfiguration of Resources in FCR
38(12)
2.4.1 Statically Reconfigurable FCR
38(1)
2.4.2 Dynamically Reconfigurable FCR
39(2)
2.4.3 Efficiency of Static and Dynamic Reconfiguration of the FCR
41(9)
2.5 Spatial versus Temporal Partitioning of Resources in an FCR
50(15)
2.5.1 Statically Configurable FCR with Spatial Partitioning of Resources
53(1)
2.5.2 Run Time Reconfigurable FCR with Spatial and Temporal Partitioning of Resources
54(3)
2.5.3 Non-Run-Time Reconfigurable FCR with Temporal Partitioning of Resources
57(5)
2.5.4 Dependence of the Amount of Temporally Partitioned Resources and Performance on Task Segmentation Granularity
62(3)
2.6 Summary
65(2)
Exercises and Problems
67(2)
References
69(2)
3 Architecture of the On-Chip Processing Elements 71(26)
3.1 Introduction
71(1)
3.2 Architecture of the Fine-Grained Configurable Processing Elements
72(11)
3.3 Architecture of the Coarse-Grained Configurable Processing Elements
83(5)
3.4 Architecture of the Hybrid Programmable Processing Elements
88(4)
3.5 Summary
92(1)
Exercises and Problems
93(1)
References
94(3)
4 Reconfigurable Communication Infrastructure in the FCR 97(26)
4.1 Introduction
97(1)
4.2 Organization of the On-Chip Communication Infrastructure
98(1)
4.3 Fine-Grained On-Chip Routing Elements in the FCR
99(2)
4.4 Coarse-Grained On-Chip Routing Elements in the FCR
101(2)
4.5 Fine-Grained On-Chip Configurable Input/Output Elements
103(1)
4.6 Generic Organization of Input and Output Buffers for PCB Interface
104(5)
4.7 Generic Organization of Output Buffers for Dynamic Links (Buses)
109(3)
4.8 Reduction of Electromagnetic Noise and Crosstalk in Data Transfer Lines
112(2)
4.9 Increasing Bandwidth Using DDR Transmission
114(3)
4.10 Coarse-Grained Interface Elements for On-Board Communication
117(2)
4.11 Summary
119(1)
Exercises and Problems
119(1)
References
120(3)
5 System-Level Organization of the FCR 123(24)
5.1 Introduction
123(1)
5.2 FCR Organization Based on Static Links between PLD-Nodes
124(5)
5.3 Organization of Dynamic System-Level Network in the Multi-PLD FCR
129(12)
5.4 Organization of the Hybrid FCR with Programmable Processing Elements
135(1)
5.4.1 Separation of the Low-Bandwidth Interface Part of the System
135(2)
5.4.2 Simplification of Design Using Macrofunction-Specific PPEs
137(4)
5.4.3 Increasing the Reliability by the Distribution of Functionality on the Off-Chip PPEs
141(1)
5.5 Organization of the Multiboard Communication Network
141(1)
5.6 Summary
142(1)
Exercises and Problems
143(2)
References
145(2)
6 Configuration Memory and Architecture Virtualization in RCS 147(14)
6.1 Introduction
147(1)
6.2 Generic Organization of Configuration Memory Hierarchy in the RCS
148(3)
6.3 Concept of Virtualization of Hardware Resources in the RCS
151(6)
6.4 Summary
157(1)
Exercises and Problems
158(1)
References
159(2)
7 Reconfiguration Process Organization in the On-Chip Level of a Reconfigurable Computing System 161(26)
7.1 Introduction
161(1)
7.2 Reconfiguration of the On-Chip Resources in the RCS
162(1)
7.3 Partitioning the On-Chip Field of Configurable Resources
162(1)
7.4 Partitioning the On-Chip Configuration Memory for Partial Reconfiguration
163(5)
7.5 Reconfiguration Process and Configuration Bit-File Structure
168(5)
7.6 Relationship between Reconfiguration Time and Organization of Configuration Port and Bus
173(3)
7.7 Self-Reconfiguration of the On-Chip FCR and On-Chip Configuration Port
176(2)
7.8 Organization of the On-Chip Configuration Cache Memory
178(2)
7.9 Organization of the Internal Configuration Controller-Loader
180(3)
7.10 Summary
183(1)
Exercises and Problems
183(2)
References
185(2)
8 RCS Architecture Configuration and Runtime Reconfiguration 187(28)
8.1 Introduction
187(1)
8.2 Methods of Start-Up Configuration of the FCR at a System Level
188(1)
8.3 Serial Daisy-Chain Configuration Scheme
189(3)
8.4 Serial and Parallel Ganged Configuration of Multiple PLDs
192(2)
8.5 Parallel Daisy-Chain Configuration Scheme
194(1)
8.6 Parallel Passive Configuration Scheme
195(1)
8.7 Multibus Configuration Scheme for Multiple PLDs
195(4)
8.8 Preconfiguration of Single or Multiple PLDs
199(1)
8.9 Organization of Runtime Reconfiguration of the FCR at a System Level
199(2)
8.10 Multiboot Runtime Self-Reconfiguration of Single and Multiple PLDs
201(2)
8.11 Multiboot Runtime Reconfiguration with Distributed External Control
203(2)
8.12 Multiboot Runtime Reconfiguration with Centralized External Control
205(2)
8.13 Partial Runtime Reconfiguration with Centralized External Control
207(2)
8.14 Partial Runtime Reconfiguration with Distributed Control
209(2)
8.15 Summary
211(1)
Exercises and Problems
212(2)
References
214(1)
9 Virtualization of the Architectural Components of a System-on-Chip 215(44)
9.1 Introduction
215(1)
9.2 General Organization of the Task Execution Process
216(2)
9.3 Segmentation of a Task and Concept of Functional Segment
218(3)
9.4 Segmentation according to Specification and Performance Requirements
221(2)
9.5 Segmentation according to Mode-Switching Time and System Constraints
223(2)
9.6 Implementation of Functional Segments in the Form of Virtual Components
225(4)
9.7 Computation Acceleration Exploiting Different Sources of Parallelism
229(1)
9.8 Computation Acceleration Using Pipelined Processing Circuits
230(4)
9.9 Computation Acceleration Exploiting Control-Flow Parallelism
234(3)
9.10 Computation Acceleration by Proper Resource Binding
237(4)
9.11 Computation Acceleration Using Data Structure Segmentation
241(2)
9.12 Organization of the Virtual Hardware Component
243(6)
9.13 Summary
249(1)
Exercises and Problems
250(7)
References
257(2)
10 Virtualization of Reconfigurable Computing System Architecture 259(50)
10.1 Introduction
259(1)
10.2 General Organization of the RCS Architecture
260(3)
10.3 Concept of ASVP and Hardware Components Integration
263(5)
10.4 ASVP with Statically Integrated Hardware Components
268(3)
10.5 ASVP with Dynamically Integrated Software and Hardware Components
271(5)
10.6 ASVP with Temporarily Integrated Hardware Components
276(10)
10.7 ASVP with Spatially Integrated Hardware Components
286(12)
10.8 Summary
298(2)
Exercises and Problems
300(7)
References
307(2)
Index 309
Lev Kirischian, Ph.D, P.Eng, Member IEEE, has been affiliated with Ryerson University, Canada for 18 years. His research involves dynamically reconfigurable computing systems, automated architectural synthesis of data-stream processors, and workload-adaptive and self-healing reconfigurable architectures. He participated in the research and development of the first-generation Soviet supercomputers with reconfigurable architectures in the 1980s, FPGA-based segment of COFDM modulation technology for digital audio/video broadcasting systems for satellite and terrestrial networks (used in the SiriusXM satellite radio network), workload adaptive and self-restorable space-borne embedded computer platforms, and 3D-panoramic machine vision systems, among other technologies. In the last decade, he has developed and taught several courses associated with high-performance and reconfigurable computing as well as high-level synthesis of application-specific processors.
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