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E-book: System-on-Chip Test Architectures: Nanometer Design for Testability

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Charles E. Stroud (Auburn University, Auburn, AL, U.S.A.), Nur A. Touba (University of Texas, Austin, TX, U.S.A.), Laung-Terng Wang (SynTest Technologies, Inc., Sunnyvale, CA, USA)

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Series: Systems on Silicon
Pub. Date: 28-Jul-2010
Publisher: Morgan Kaufmann Publishers In
Language: eng
ISBN-13: 9780080556802

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Electrical engineering

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Format: PDF+DRM
Series: Systems on Silicon
Pub. Date: 28-Jul-2010
Publisher: Morgan Kaufmann Publishers In
Language: eng
ISBN-13: 9780080556802

Other books in subject:

Electrical engineering

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Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

More info

The comprehensive guide to modern system-on-chip testing and design for testability from bestselling author L.-T Wang!

Preface

xxi

In the Classroom

xxvii

Acknowledgments

xxix

Contributors

xxxi

About the Editors

xxxv

Introduction

(40)

Laung-Terng (L.-T.) Wang

Charles E. Stroud

Nur A. Touba

Importance of System-on-Chip Testing

(6)

Yield and Reject Rate

(1)

Reliability and System Availability

(2)

Basics of SOC Testing

(12)

Boundary Scan (IEEE 1149.1 Standard)

(2)

Boundary Scan Extension (IEEE 1149.6 Standard)

(2)

Boundary-Scan Accessible Embedded Instruments (IEEE P1687)

(1)

Core-Based Testing (IEEE 1500 Standard)

(4)

Analog Boundary Scan (IEEE 1149.4 Standard)

(3)

Basics of Memory Testing

(4)

SOC Design Examples

(6)

BioMEMS Sensor

(2)

Network-on-Chip Processor

(3)

About This Book

(3)

DFT Architectures

(1)

New Fault Models and Advanced Techniques

(1)

Yield and Reliability Enhancement

(1)

Nanotechnology Testing Aspects

(1)

Exercises

(8)

Acknowledgments

(1)

References

(5)

Digital Test Architectures

(82)

Laung-Terng (L.-T.) Wang

Introduction

(2)

Scan Design

(14)

Scan Architectures

(1)

Muxed-D Scan Design

(2)

Clocked-Scan Design

(1)

LSSD Scan Design

(1)

Enhanced-Scan Design

(2)

Low-Power Scan Architectures

(1)

Reduced-Voltage Low-Power Scan Design

(1)

Reduced-Frequency Low-Power Scan Design

(1)

Multi-Phase or Multi-Duty Low-Power Scan Design

(1)

Bandwidth-Matching Low-Power Scan Design

(1)

Hybrid Low-Power Scan Design

(1)

At-Speed Scan Architectures

(5)

Logic Built-In Self-Test

(19)

Logic BIST Architectures

(1)

Self-Testing Using MISR and Parallel SRSG (STUMPS)

(1)

Concurrent Built-In Logic Block Observer (CBILBO)

(2)

Coverage-Driven Logic BIST Architectures

(1)

Weighted Pattern Generation

(1)

Test Point Insertion

(2)

Mixed-Mode BIST

(1)

Hybrid BIST

(1)

Low-Power Logic BIST Architectures

(1)

Low-Transition BIST Design

(1)

Test-Vector-Inhibiting BIST Design

(1)

Modified LFSR Low-Power BIST Design

(1)

At-Speed Logic BIST Architectures

(1)

Single-Capture

(2)

Skewed-Load

(3)

Double-Capture

(2)

Industry Practices

(1)

Test Compression

(21)

Circuits for Test Stimulus Compression

(1)

Linear-Decompression-Based Schemes

(4)

Broadcast-Scan-Based Schemes

(4)

Comparison

(2)

Circuits for Test Response Compaction

(1)

Space Compaction

(4)

Time Compaction

(1)

Mixed Time and Space Compaction

(1)

Low-Power Test Compression Architectures

(1)

Industry Practices

(2)

Random-Access Scan Design

(9)

Random-Access Scan Architectures

(2)

Progressive Random-Access Scan Design

100

(1)

Shift-Addressable Random-Access Scan Design

101

(2)

Test Compression RAS Architectures

103

(2)

At-Speed RAS Architectures

105

(1)

Concluding Remarks

106

(1)

Exercises

106

(17)

Acknowledgments

110

(1)

References

111

(12)

Fault-Tolerant Design

123

(48)

Nur A. Touba

Introduction

123

(1)

Fundamentals of Fault Tolerance

124

(5)

Reliability

125

(1)

Mean Time to Failure (MTTF)

126

(1)

Maintainability

127

(1)

Availability

127

(2)

Fundamentals of Coding Theory

129

(13)

Linear Block Codes

129

(6)

Unidirectional Codes

135

(1)

Two-Rail Codes

135

(1)

Berger Codes

136

(1)

Constant Weight Codes

136

(1)

Cyclic Codes

137

(5)

Fault Tolerance Schemes

142

(21)

Hardware Redundancy

142

(1)

Static Redundancy

142

(4)

Dynamic Redundancy

146

(2)

Hybrid Redundancy

148

(2)

Time Redundancy

150

(1)

Repeated Execution

150

(1)

Multiple Sampling of Outputs

151

(1)

Diverse Recomputation

152

(1)

Information Redundancy

153

(1)

Error Detection

153

(7)

Error Correction

160

(3)

Industry Practices

163

(2)

Concluding Remarks

165

(1)

Exercises

165

(6)

Acknowledgments

168

(1)

References

168

(3)

System/Network-on-Chip Test Architectures

171

(54)

Chunsheng Liu

Krishnendu Chakrabarty

Wen-Ben Jone

Introduction

172

(3)

System-on-Chip (SOC) Testing

175

(17)

Modular Testing of SOCs

175

(2)

Wrapper Design and Optimization

177

(2)

TAM Design and Optimization

179

(2)

Test Scheduling

181

(4)

Modular Testing of Mixed-Signal SOCs

185

(3)

Modular Testing of Hierarchical SOCs

188

(3)

Wafer-Sort Optimization for Core-Based SOCs

191

(1)

Network-on-Chip (NOC) Testing

192

(17)

NOC Architectures

192

(2)

Testing of Embedded Cores

194

(1)

Reuse of On-Chip Network for Testing

194

(2)

Test Scheduling

196

(1)

Test Access Methods and Test Interface

197

(1)

Efficient Reuse of Network

198

(4)

Power-Aware and Thermal-Aware Testing

202

(1)

Testing of On-Chip Networks

203

(1)

Testing of Interconnect Infrastructures

203

(2)

Testing of Routers

205

(3)

Testing of Network Interfaces and Integrated System Testing

208

(1)

Design and Test Practice: Case Studies

209

(6)

SOC Testing for PNX8550 System Chip

210

(2)

NOC Testing for a High-End TV System

212

(3)

Concluding Remarks

215

(1)

Exercises

216

(9)

Acknowledgments

217

(1)

References

217

(8)

SIP Test Architectures

225

(38)

Philippe Cauvet

Michel Renovell

Serge Bernard

Introduction

226

(9)

SIP Definition

226

(1)

SIP Examples

227

(3)

Yield and Quality Challenges

230

(3)

Test Strategy

233

(2)

Bare Die Test

235

(7)

Mechanical Probing Techniques

235

(2)

Electrical Probing Techniques

237

(3)

Reliability Screens

240

(2)

Functional System Test

242

(4)

Path-Based Testing

242

(3)

Loopback Techniques: DFT and DSP

245

(1)

Test of Embedded Components

246

(11)

SIP Test Access Port

247

(3)

Interconnections

250

(1)

Digital and Memory Dies

251

(2)

Analog and RF Components

253

(1)

Test Equipment Issues

253

(1)

Test of Analog, Mixed-Signal, and RF Dies

254

(1)

MEMS

255

(2)

Concluding Remarks

257

(1)

Exercises

257

(6)

Acknowledgments

258

(1)

References

258

(5)

Delay Testing

263

(44)

Duncan M. (Hank) Walker

Michael S. Hsiao

Introduction

263

(2)

Delay Test Application

265

(4)

Enhanced Scan

266

(1)

Muxed-D Scan

266

(1)

Scan Clocking

266

(2)

Faster-Than-At-Speed Testing

268

(1)

Delay Fault Models

269

(7)

Transition Fault Model

269

(1)

Inline-Delay Fault Model

270

(1)

Gate-Delay Fault Model

270

(1)

Path-Delay Fault Model

270

(1)

Defect-Based Delay Fault Models

271

(5)

Delay Test Sensitization

276

(1)

Delay Fault Simulation

277

(3)

Transition Fault Simulation

277

(1)

Gate/Line Delay Fault Simulation

277

(1)

Path-Delay Fault Simulation

278

(1)

Defect-Based Delay Fault Model Simulation

278

(2)

Delay Fault Test Generation

280

(8)

Transition/Inline Fault ATPG

280

(2)

Gate-Delay Fault ATPG

282

(1)

Path-Delay Fault ATPG

282

(1)

K Longest Paths per Gate (KLPG) ATPG

283

(5)

Pseudo-Functional Testing to Avoid Over-Testing

288

(6)

Computing Constraints

290

(1)

Pair-Wise Constraints

291

(1)

Multiliteral Constraints

291

(2)

Constrained ATPG

293

(1)

Concluding Remarks

294

(1)

Exercises

295

(12)

Acknowledgments

299

(1)

References

300

(7)

Low-Power Testing

307

(44)

Patrick Girard

Xiaoqing Wen

Nur A. Touba

Introduction

307

(2)

Energy and Power Modeling

309

(4)

Basics of Circuit Theory

310

(1)

Terminology

311

(1)

Test-Power Modeling and Evaluation

312

(1)

Test Power Issues

313

(3)

Thermal Effects

314

(1)

Noise Phenomena

314

(1)

Miscellaneous Issues

315

(1)

Low-Power Scan Testing

316

(12)

Basics of Scan Testing

316

(2)

ATPG and X-Filling Techniques

318

(2)

Low-Power Test Vector Compaction

320

(1)

Shift Control Techniques

321

(1)

Scan Cell Ordering

322

(2)

Scan Architecture Modification

324

(2)

Scan Clock Splitting

326

(2)

Low-Power Built-in Self-Test

328

(7)

Basics of Logic BIST

328

(1)

LFSR Tuning

329

(1)

Low-Power Test Pattern Generators

330

(1)

Vector Filtering BIST

331

(1)

Circuit Partitioning

332

(2)

Power-Aware Test Scheduling

334

(1)

Low-Power Test Data Compression

335

(4)

Coding-Based Schemes

336

(1)

Linear-Decompression-Based Schemes

336

(1)

Broadcast-Scan-Based Schemes

337

(2)

Low-Power RAM Testing

339

(2)

Concluding Remarks

341

(1)

Exercises

342

(9)

Acknowledgments

344

(1)

References

344

(7)

Coping with Physical Failures, Soft Errors, and Reliability Issues

351

(72)

Laung-Terng (L.-T.) Wang

Mehrdad Nourani

T. M. Mak

Introduction

352

(2)

Signal Integrity

354

(16)

Basic Concept of Integrity Loss

354

(2)

Sources of Integrity Loss

356

(1)

Interconnects

356

(2)

Power Supply Noise

358

(1)

Process Variations

358

(2)

Integrity Loss Sensors/Monitors

360

(1)

Current Sensor

360

(1)

Power Supply Noise Monitor

361

(1)

Noise Detector (ND) Sensor

362

(1)

Integrity Loss Sensor (ILS)

362

(1)

Jitter Monitor

363

(1)

Process Variation Sensor

364

(1)

Readout Architectures

365

(1)

BIST-Based Architecture

365

(2)

Scan-Based Architecture

367

(1)

PV-Test Architecture

368

(2)

Manufacturing Defects, Process Variations, and Reliability

370

(16)

Fault Detection

370

(1)

Structural Tests

371

(1)

Defect-Based Tests

372

(6)

Functional Tests

378

(1)

Reliability Stress

379

(2)

Redundancy and Memory Repair

381

(1)

Process Sensors and Adaptive Design

382

(1)

Process Variation Sensor

383

(1)

Thermal Sensor

383

(2)

Dynamic Voltage Scaling

385

(1)

Soft Errors

386

(16)

Sources of Soft Errors and SER Trends

387

(3)

Coping with Soft Errors

390

(1)

Fault Tolerance

390

(4)

Error-Resilient Microarchitectures

394

(4)

Soft Error Mitigation

398

(4)

Defect and Error Tolerance

402

(5)

Defect Tolerance

404

(1)

Error Tolerance

405

(2)

Concluding Remarks

407

(1)

Exercises

407

(16)

Acknowledgments

409

(1)

References

409

(14)

Design for Manufacturability and Yield

423

(40)

Robert C. Aitken

Introduction

423

(3)

Yield

426

(1)

Components of Yield

427

(3)

Yield Models

428

(1)

Yield and Repair

429

(1)

Photolithography

430

(3)

DFM and DFY

433

(12)

Photolithography

435

(4)

Critical Area

439

(2)

Yield Variation over Time

441

(3)

DFT and DFM/DFY

444

(1)

Variability

445

(4)

Sources of Variability

445

(1)

Deterministic versus Random Variability

446

(2)

Variability versus Defectivity

448

(1)

Putting It All Together

449

(1)

Metrics for DFX

449

(7)

The Ideal Case

450

(2)

Potential DFY Metrics

452

(1)

Critical Area

452

(1)

RET-Based Metrics

452

(2)

Example DRC-Based Metrics for DFM

454

(2)

Concluding Remarks

456

(1)

Exercises

457

(6)

Acknowledgments

458

(1)

References

459

(4)

Design for Debug and Diagnosis

463

(42)

T. M. Mak

Srikanth Venkataraman

Introduction

463

(5)

What Are Debug and Diagnosis?

464

(1)

Where Is Diagnosis Used?

465

(1)

IC-Level Debug and Diagnosis

465

(1)

Silicon Debug versus Defect Diagnosis

466

(1)

Design for Debug and Diagnosis

467

(1)

Logic Design for Debug and Diagnosis (DFD) Structures

468

(8)

Scan

468

(1)

Observation-Only Scan

469

(2)

Observation Points with Multiplexers

471

(1)

Array Dump and Trace Logic Analyzer

472

(1)

Clock Control

473

(2)

Partitioning, Isolation, and De-featuring

475

(1)

Reconfigurable Logic

476

(1)

Probing Technologies

476

(11)

Mechanical Probing

477

(1)

Injection-Based Probing

478

(1)

E-beam Probing

478

(1)

Laser Voltage Probing

479

(4)

Emission-Based Probing

483

(1)

Infrared Emission Microscopy (IREM)

483

(2)

Picosecond Imaging Circuit Analysis (PICA)

485

(1)

Time Resolved Emissions (TRE)

486

(1)

Circuit Editing

487

(3)

Focused Ion Beam

487

(1)

Layout-Database-Driven Navigation System

488

(1)

Spare Gates and Spare Wires

489

(1)

Physical DFD Structures

490

(2)

Physical DFD for Pico-Probing

490

(1)

Physical DFD for E-Beam

491

(1)

Physical DFD for FIB and Probing

492

(1)

Diagnosis and Debug Process

492

(6)

Diagnosis Techniques and Strategies

495

(1)

Silicon Debug Process and Flow

496

(1)

Debug Techniques and Methodology

497

(1)

Concluding Remarks

498

(1)

Exercises

499

(6)

Acknowledgments

500

(1)

References

500

(5)

Software-Based Self-Testing

505

(44)

Jiun-Lang Huang

Kwang-Ting (Tim) Cheng

Introduction

506

(1)

Software-Based Self-Testing Paradigm

507

(3)

Self-Test Flow

508

(1)

Comparison with Structural BIST

509

(1)

Processor Functional Fault Self-Testing

510

(6)

Processor Model

510

(2)

Functional-Level Fault Models

512

(1)

Test Generation Procedures

513

(1)

Test Generation for Register Decoding Fault

513

(1)

Test Generation for Instruction Decoding and Control Fault

514

(1)

Test Generation for Data Transfer and Storage Function

515

(1)

Test Generation for Data Manipulation Function

516

(1)

Test Generation Complexity

516

(1)

Processor Structural Fault Self-Testing

516

(14)

Test Flow

516

(1)

Test Preparation

516

(1)

Self-Testing

517

(1)

Stuck-At Fault Testing

518

(1)

Instruction-Imposed I/O Constraint Extraction

518

(1)

Constrained Component Test Generation

519

(2)

Test Program Synthesis

521

(1)

Processor Self-Testing

522

(1)

Test Program Synthesis Using Virtual Constraint Circuits (VCCs)

523

(3)

Delay Fault Testing

526

(1)

Functionally Untestable Delay Faults

526

(1)

Constraint Extraction

527

(1)

Test Program Generation

528

(1)

Functional Random Instruction Testing

529

(1)

Processor Self-Diagnosis

530

(3)

Challenges to SBST-Based Processor Diagnosis

530

(1)

Diagnostic Test Program Generation

531

(2)

Testing Global Interconnect

533

(3)

Maximum Aggressor (MA) Fault Model

533

(1)

Processor-Based Address and Data Bus Testing

534

(1)

Data Bus Testing

534

(1)

Address Bus Testing

535

(1)

Processor-Based Functional MA Testing

536

(1)

Testing Nonprogrammable Cores

536

(2)

Preprocessing Phase

538

(1)

Core Test Phase

538

(1)

Instruction-Level DFT

538

(3)

Instruction-Level DFT Concept

538

(1)

Testability Instructions

539

(2)

Test Optimization Instructions

541

(1)

DSP-Based Analog/Mixed-Signal Component Testing

541

(2)

Concluding Remarks

543

(1)

Exercises

544

(5)

Acknowledgments

545

(1)

References

545

(4)

Field Programmable Gate Array Testing

549

(42)

Charles E. Stroud

Overview of FPGAs

549

(9)

Architecture

550

(4)

Configuration

554

(2)

The Testing Problem

556

(2)

Testing Approaches

558

(4)

External Testing and Built-in Self-Test

559

(1)

Online and Offline Testing

560

(1)

Application Dependent and Independent Testing

561

(1)

BIST of Programmable Resources

562

(21)

Logic Resources

563

(4)

Programmable Logic Blocks

567

(3)

Input/Output Cells

570

(1)

Specialized Cores

571

(4)

Diagnosis

575

(3)

Interconnect Resources

578

(5)

Embedded Processor-Based Testing

583

(2)

Concluding Remarks

585

(1)

Exercises

586

(5)

Acknowledgments

587

(1)

References

587

(4)

MEMS Testing

591

(62)

Ramesh Ramadoss

Robert Dean

Xingguo Xiong

Introduction

592

(1)

MEMS Testing Considerations

593

(1)

Test Methods and Instrumentation for MEMS

594

(15)

Electrical Test

595

(1)

Optical Test Methods

596

(2)

Material Property Measurements

598

(1)

Failure Modes and Analysis

599

(1)

Mechanical Test Methods

600

(7)

Environmental Testing

607

(2)

RF MEMS Devices

609

(5)

RF MEMS Switches

610

(1)

RF MEMS Resonators

611

(3)

Optical MEMS Devices

614

(2)

Fluidic MEMS Devices

616

(4)

MEMS Pressure Sensor

617

(1)

MEMS Humidity Sensor

618

(2)

Dynamic MEMS Devices

620

(5)

MEMS Microphone

620

(1)

MEMS Accelerometer

621

(1)

MEMS Gyroscope

622

(3)

Testing Digital Microfluidic Biochips

625

(8)

Overview of Digital Microfluidic Biochips

626

(1)

Fault Modeling

627

(1)

Test Techniques

628

(3)

Application to a Fabricated Biochip

631

(2)

DFT and BIST for MEMS

633

(10)

Overview of DFT and BIST Techniques

633

(4)

MEMS BIST Examples

637

(6)

Concluding Remarks

643

(1)

Exercises

644

(9)

Acknowledgments

646

(1)

References

646

(7)

High-Speed I/O Interfaces

653

(50)

Mike Peng Li

T. M. Male

Kwang-Ting (Tim) Cheng

Introduction

654

(3)

High-Speed I/O Architectures

657

(11)

Global Clock I/O Architectures

657

(1)

Source Synchronous I/O Architectures

658

(2)

Embedded Clock I/O Architectures

660

(1)

Jitter Components

661

(1)

Jitter Separation

662

(4)

Jitter, Noise, and Bit-Error-Rate Interactions

666

(2)

Testing of I/O Interfaces

668

(12)

Testing of Global Clock I/O

669

(1)

Testing of Source Synchronous I/O

669

(2)

Testing of Embedded Clock High-Speed Serial I/O

671

(1)

Transmitter

671

(2)

Channel or Medium

673

(2)

Receiver

675

(2)

Reference Clock

677

(1)

System-Level Bit-Error-Rate Estimation

678

(1)

Tester Apparatus Considerations

678

(2)

DFT-Assisted Testing

680

(10)

AC Loopback Testing

681

(2)

High-Speed Serial-Link Loopback Testing

683

(3)

Testing the Equalizers

686

(4)

System-Level Interconnect Testing

690

(4)

Interconnect Testing with Boundary Scan

690

(1)

Interconnect Testing with High-Speed Boundary Scan

691

(2)

Interconnect Built-in Self-Test

693

(1)

Future Challenges

694

(1)

Concluding Remarks

695

(1)

Exercises

696

(7)

Acknowledgments

697

(1)

References

697

(6)

Analog and Mixed-Signal Test Architectures

703

(42)

F. Foster Dai

Charles E. Stroud

Introduction

704

(1)

Analog Functional Testing

705

(15)

Frequency Response Testing

705

(2)

Linearity Testing

707

(2)

Signal-to-Noise Ratio Testing

709

(1)

Quantization Noise

710

(2)

Phase Noise

712

(3)

Noise in Phase-Locked Loops

715

(1)

In-Band PLL Phase Noise

716

(2)

Out-Band PLL Phase Noise

718

(1)

Optimal Loop Setting

718

(1)

DAC Nonlinearity Testing

719

(1)

Analog and Mixed-Signal Test Architectures

720

(4)

Defect-Oriented Mixed-Signal BIST Approaches

724

(3)

FFT-Based Mixed-Signal BIST

727

(6)

FFT

727

(2)

Inverse FFT

729

(1)

FFT-Based BIST Architecture

729

(1)

FFT-Based Output Response Analysis

730

(1)

FFT-Based Test Pattern Generation

731

(2)

Direct Digital Synthesis BIST

733

(6)

DOS-Based BIST Architecture

734

(2)

Frequency Response Test and Measurement

736

(2)

Linearity Test and Measurement

738

(1)

SNR and Noise Figure Measurement

739

(1)

Concluding Remarks

739

(1)

Exercises

740

(5)

Acknowledgments

741

(1)

References

741

(4)

RF Testing

745

(46)

Soumendu Bhattacharya

Abhijit Chatterjee

Introduction

746

(4)

RF Basics

746

(2)

RF Applications

748

(2)

Key Specifications for RF Systems

750

(26)

Test Instrumentation

750

(1)

Spectrum Analyzer

751

(1)

Network Analyzer

752

(1)

Noise Figure Meter

753

(2)

Phase Meter

755

(1)

Test Flow in Industry

755

(1)

Design and Fabrication

756

(1)

Characterization Test

756

(1)

Production Test

756

(1)

Characterization Test and Production Test

757

(1)

Accuracy

757

(1)

Time Required for Testing

758

(1)

Cost of Testing

758

(1)

Circuit-Level Specifications

758

(1)

Gain

759

(1)

Harmonics and Third-Order Intercept Point (IP3)

759

(4)

1-dB Compression Point (P_ldB)

763

(1)

Total Harmonic Distortion (THD)

763

(1)

Gain Flatness

764

(1)

Noise Figure

765

(2)

Sensitivity and Dynamic Range

767

(1)

Local Oscillator Leakage

768

(1)

Phase Noise

768

(1)

Adjacent Channel Power Ratio

769

(1)

System-Level Specifications

770

(1)

I-Q Mismatch

770

(1)

Error Vector Magnitude

771

(1)

Modulation Error Ratio

772

(1)

Bit Error Rate

773

(1)

Structure of RF Systems

774

(2)

Test Hardware: Tester and DIB/PIB

776

(3)

Repeatability and Accuracy

779

(3)

Industry Practices for High-Volume Manufacturing

782

(3)

Test Cost Analysis

783

(1)

Key Trends

784

(1)

Concluding Remarks

785

(1)

Exercises

786

(5)

Acknowledgments

787

(1)

References

788

(3)

Testing Aspects of Nanotechnology Trends

791

(42)

Mehdi B. Tahoori

Niraj K. Jha

R. Iris Bahar

Introduction

792

(2)

Resonant Tunneling Diodes and Quantum-Dot Cellular Automata

794

(13)

Testing Threshold Networks with Application to RTDs

795

(4)

Testing Majority Networks with Application to QCA

799

(8)

Crossbar Array Architectures

807

(8)

Hybrid Nanoscale/CMOS Structures

810

(1)

The nanoPLA

810

(3)

Molecular CMOS (CMOL)

813

(2)

Built-in Self-Test

815

(5)

Simultaneous Configuration and Test

817

(3)

Carbon Nanotube (CNT) Field Effect Transistors

820

(6)

Imperfection-Immune Circuits for Misaligned CNTs

820

(4)

Robust Circuits for Metallic CNTs

824

(2)

Concluding Remarks

826

(7)

Acknowledgments

826

(1)

References

827

(6)

Index

833

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

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