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E-raamat: 3D IC Integration and Packaging

  • Formaat: 480 pages
  • Ilmumisaeg: 06-Jul-2015
  • Kirjastus: McGraw-Hill Professional
  • Keel: eng
  • ISBN-13: 9780071848077
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3D IC Integration and PackagingSuurem pilt
  • Formaat: 480 pages
  • Ilmumisaeg: 06-Jul-2015
  • Kirjastus: McGraw-Hill Professional
  • Keel: eng
  • ISBN-13: 9780071848077
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A comprehensive guide to 3D IC integration and packaging technology

3D IC Integration and Packaging fully explains the latest microelectronics techniques for increasing chip density and maximizing performance while reducing power consumption. Based on a course developed by its author, this practical guide offers real-world problem-solving methods and teaches the trade-offs inherent in making system-level decisions. Explore key enabling technologies such as TSV, thin-wafer strength measurement and handling, microsolder bumping, redistribution layers, interposers, wafer-to-wafer bonding, chip-to-wafer bonding, 3D IC and MEMS, LED, and complementary metal-oxide semiconductor image sensors integration. Assembly, thermal management, and reliability are covered in complete detail.



3D IC Integration and Packaging covers:



 3D integration for semiconductor IC packaging  Through-silicon vias modeling and testing  Stress sensors for thin-wafer handling and strength measurement  Package substrate technologies  Microbump fabrication, assembly, and reliability  3D Si integration  2.5D/3D IC integration  3D IC integration with passive interposer  Thermal management of 2.5D/3D IC integration  Embedded 3D hybrid integration  3D LED and IC integration  3D MEMS and IC integration  3D CMOS image sensors and IC integration  PoP, chip-to-chip interconnects, and embedded fan-out WLP
Preface xvii
Acknowledgments xxi
1 3D Integration for Semiconductor IC Packaging 1(28)
1.1 Introduction
1(1)
1.2 3D Integration
1(3)
1.3 3D IC Packaging
4(1)
1.4 3D Si Integration
5(2)
1.5 3D IC Integration
7(6)
1.5.1 Hybrid Memory Cube
7(1)
1.5.2 Wide I/O DRAM and Wide I/O 2
8(2)
1.5.3 High Bandwidth Memory
10(1)
1.5.4 Wide I/O Memory (or Logic-on-Logic)
10(1)
1.5.5 Passive Interposer (2.5D IC Integration)
10(3)
1.6 Supply Chains before the TSV Era
13(1)
1.6.1 FEOL (Front-End-of-Line)
13(1)
1.6.2 BEOL (Back-End-of-Line)
13(1)
1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)
13(1)
1.7 Supply Chains for the TSV Era-Who Makes the TSV?
13(1)
1.7.1 TSVs Fabricated by the Via-First Process
13(1)
1.7.2 TSVs Fabricated by the Via-Middle Process
13(1)
1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process
13(1)
1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process
13(1)
1.7.5 How About the Passive TSV Interposers?
14(1)
1.7.6 Who Wants to Fabricate the TSV for Passive Interposers?
14(1)
1.7.7 Summary and Recommendations
14(1)
1.8 Supply Chains for the TSV Era-Who Does the MEOL, Assembly, and Test?
14(5)
1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process
14(2)
1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process
16(1)
1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process
16(1)
1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers
17(1)
1.8.5 Summary and Recommendations
18(1)
1.9 CMOS Images Sensors with TSVs
19(3)
1.9.1 Toshiba's Dynastron™
19(1)
1.9.2 STMicroelectronics' VGA CIS Camera Module
19(1)
1.9.3 Samsung's S5K4E5YX BSI CIS
20(1)
1.9.4 Toshiba's HEW4 BSI TCM5103PL
20(1)
1.9.5 Nemotek's CIS
21(1)
1.9.6 SONY'S ISX014 Stacked Camera Sensor
22(1)
1.10 MEMS with TSVs
22(2)
1.10.1 STMicroelectronics' MEMS Inertial Sensors
22(1)
1.10.2 Discera's MEME Resonator
22(2)
1.10.3 Avago's FBAR MEMS Filter
24(1)
1.11 References
24(5)
2 Through-Silicon Vias Modeling and Testing 29(38)
2.1 Introduction
29(1)
2.2 Electrical Modeling of TSVs
29(11)
2.2.1 Analytic Model and Equations for a Generic TSV Structure
29(3)
2.2.2 Verification of the Proposed TSV Model in Frequency Domain
32(3)
2.2.3 Verification of the Proposed TSV Model in Time Domain
35(3)
2.2.4 TSV Electrical Design Guideline
38(1)
2.2.5 Summary and Recommendations
38(2)
2.3 Thermal Modeling of TSVs
40(13)
2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction
40(3)
2.3.2 Thermal Behavior of a TSV Cell
43(4)
2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations
47(1)
2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations
48(3)
2.3.5 Summary and Recommendations
51(2)
2.4 Mechanical Modeling and Testing of TSVs
53(11)
2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si
53(2)
2.4.2 Experimental Results on Cu Pumping during Manufacturing
55(3)
2.4.3 Cu Pumping under Thermal Shock Cycling
58(3)
2.4.4 Keep-Out-Zone of Cu-Filled TSVs
61(3)
2.4.5 Summary and Recommendations
64(1)
2.5 References
64(3)
3 Stress Sensors for Thin-Wafer Handling and Strength Measurement 67(26)
3.1 Introduction
67(1)
3.2 Design and Fabrication of Piezoresistive Stress Sensors
67(6)
3.2.1 Design of Piezoresistive Stress Sensors
68(1)
3.2.2 Fabrication of the Stress Sensors
69(2)
3.2.3 Summary and Recommendations
71(2)
3.3 Application of Stress Sensors in Thin-Wafer Handling
73(6)
3.3.1 Design, Fabrication, and Calibration of Piezoresistive Stress Sensors
73(4)
3.3.2 Stress Measurement in Wafer after Thinning
77(1)
3.3.3 Summary and Recommendations
78(1)
3.4 Application of Stress Sensors in Wafer Bumping
79(5)
3.4.1 Stresses after UBM Fabrication
79(1)
3.4.2 Stresses after Dry-Film Process
79(4)
3.4.3 Stresses after Solder Bumping Process
83(1)
3.4.4 Summary and Recommendations
84(1)
3.5 Application of Stress Sensors in Drop Test of Embedded Ultrathin Chips
84(6)
3.5.1 Test Vehicle and Fabrication
84(1)
3.5.2 Experimental Setup and Procedure
85(1)
3.5.3 In-Situ Stress Measurement Results
86(2)
3.5.4 Reliability Testing
88(1)
3.5.5 Summary and Recommendations
88(2)
3.6 References
90(3)
4 Package Substrate Technologies 93(16)
4.1 Introduction
93(1)
4.2 Package Substrate with Build-up Layers for Flip Chip 3D IC Integration
93(3)
4.2.1 Surface Laminate Circuit Technology
93(2)
4.2.2 The Trend in Package Substrate with Build-up Layers
95(1)
4.2.3 Summary and Recommendations
96(1)
4.3 Coreless Package Substrates
96(6)
4.3.1 Advantages and Disadvantages of Coreless Package Substrates
96(1)
4.3.2 Substitution of Si Interposer by Coreless Substrates
97(2)
4.3.3 Warpage Problem and Solution of Coreless Substrates
99(3)
4.3.4 Summary and Recommendations
102(1)
4.4 Recent Advance of Package Substrate with Build-up Layer
102(5)
4.4.1 Thin-Film Layers on Top of Build-up Layer of Package Substrate
102(4)
4.4.2 Warpage and Qualification Results
106(1)
4.4.3 Summary and Recommendations
107(1)
4.5 References
107(2)
5 Microbumps: Fabrication, Assembly, and Reliability 109(34)
5.1 Introduction
109(1)
5.2 Fabrication, Assembly, and Reliability of 25-µm-Pitch Microbumps
109(14)
5.2.1 Test Vehicle
109(1)
5.2.2 Structure of the Microbumps
110(2)
5.2.3 Structure of the ENIG Pads
112(1)
5.2.4 Fabrication of the 25-km-Pitch Microbumps
113(1)
5.2.5 Fabrication of ENIG Bonding Pads on Si Carrier
114(2)
5.2.6 Thermal Compression Bonding Assembly
116(4)
5.2.7 Evaluation of the Underfill
120(1)
5.2.8 Reliability Assessment
121(1)
5.2.9 Summary and Recommendations
122(1)
5.3 Fabrication, Assembly, and Reliability of 20-rim-Pitch Microbumps
123(11)
5.3.1 Test Vehicle
123(1)
5.3.2 Assembly of Test Vehicle
124(1)
5.3.3 Formation of Microjoints by Thermocompression Bonding
124(1)
5.3.4 Microgap Filling
125(1)
5.3.5 Reliability Test
126(1)
5.3.6 Reliability Test Results and Discussion
127(3)
5.3.7 Failure Mechanism of the Microjoints
130(3)
5.3.8 Summary and Recommendations
133(1)
5.4 Fabrication, Assembly, and Reliability of 15-µm-Pitch Microbumps
134(4)
5.4.1 Microbumps and UBM Pads of the Test Vehicle
134(1)
5.4.2 Assembly
135(1)
5.4.3 Assembly with CuSn Solder Microbump and ENIG Pad
136(1)
5.4.4 Assembly with CuSn Solder Microbump and CuSn Solder Microbump
136(1)
5.4.5 Evaluation of Underfill
137(1)
5.4.6 Summary and Recommendations
138(1)
5.5 References
138(5)
6 3D Si Integration 143(18)
6.1 Introduction
143(1)
6.2 The Electronic Industry
143(1)
6.3 Moore's Law and More-Than-Moore
144(1)
6.4 The Origin of 3D Integration
145(1)
6.5 Overview and Outlook of 3D Si Integration
146(8)
6.5.1 Bonding Methods for 3D Si Integration
147(1)
6.5.2 Cu-to-Cu (W2W) Bonding
148(2)
6.5.3 Cu-to-Cu (W2W) Bonding with Post-Annealing
150(1)
6.5.4 Cu-to-Cu (W2W) Bonding at Room Temperature
151(1)
6.5.5 SiO2-to-SiO2 (W2W) Bonding
151(3)
6.5.6 A Few Notes on W2W Bonding
154(1)
6.6 3D Si Integration Technology Challenges
154(1)
6.7 3D Si Integration EDA Challenges
155(1)
6.8 Summary and Recommendations
155(2)
6.9 References
157(4)
7 2.5D/3D IC Integration 161(42)
7.1 Introduction
161(1)
7.2 TSV Process for 3D IC Integration
162(3)
7.2.1 Tiny Vias on a Chip
162(1)
7.2.2 Via-First Process
163(1)
7.2.3 Via-Middle Process
163(1)
7.2.4 Via-Last from the Front-Side Process
163(1)
7.2.5 Via-Last from the Back-Side Process
163(2)
7.2.6 Summary and Recommendations
165(1)
7.3 The Potential Application of 3D IC Integration
165(1)
7.4 Memory-Chip Stacking
165(3)
7.4.1 The Chips
165(1)
7.4.2 The Potential Products
166(2)
7.4.3 Assembly Process
168(1)
7.5 Wide I/O Memory or Logic-on-Logic
168(5)
7.5.1 The Chips
168(1)
7.5.2 The Potential Products
168(3)
7.5.3 Assembly Process
171(2)
7.6 Wide I/O DRAM or Hybrid Memory Cube
173(4)
7.6.1 The Chips
173(2)
7.6.2 The Potential Products
175(1)
7.6.3 Assembly Process
176(1)
7.7 Wide I/O 2 and High Bandwidth Memory
177(1)
7.8 Wide I/O Interface (2.5D IC Integration)
178(13)
7.8.1 Real Applications of TSV/RDL Passive Interposers
178(2)
7.8.2 Fabrication of Interposers
180(1)
7.8.3 Fabrication of TSVs
181(2)
7.8.4 Fabrication of RDLs
183(1)
7.8.5 Fabrication of RDLs-Polymer/Cu-Plating Method
183(2)
7.8.6 Fabrication of RDLs-Cu Damascene Method
185(3)
7.8.7 A Note on Contact Aligner for Cu Damascene Method
188(1)
7.8.8 Back-Side Processing and Assembly
188(3)
7.8.9 Summary and Recommendations
191(1)
7.9 Thin-Wafer Handling
191(8)
7.9.1 Conventional Thin-Wafer Handling Method
192(1)
7.9.2 TI's TSV-WCSP Integration Process
192(2)
7.9.3 TSMC's Thin-Wafer Handling with Polymer
194(1)
7.9.4 TSMC's Thin-Wafer Handling without Temporary Bonding and De-Bonding
194(1)
7.9.5 Thin-Wafer Handling with a Heat-Spreader Wafer
194(3)
7.9.6 Summary and Recommendations
197(2)
7.10 References
199(4)
8 3D IC Integration with Passive Interposer 203(58)
8.1 Introduction
203(1)
8.2 3D IC Integration with TSV/RDL Interposer
203(1)
8.3 TSV/RDL Interposer with Double-Sided Chip Attachments
203(22)
8.3.1 The Structure
203(3)
8.3.2 Thermal Analysis-Boundary Conditions
206(1)
8.3.3 Thermal Analysis-TSV Equivalent Model
206(1)
8.3.4 Thermal Analysis-Solder Bump/Underfill Equivalent Model
206(1)
8.3.5 Thermal Analysis-Results
207(2)
8.3.6 Thermomechanical Analysis-Boundary Conditions
209(1)
8.3.7 Thermomechanical Analysis-Material Properties
210(1)
8.3.8 Thermomechanical Analysis-Results
211(3)
8.3.9 Fabrication of the TSV
214(2)
8.3.10 Fabrication of the Interposer with Top-Side RDLs
216(1)
8.3.11 TSV Reveal of the Cu-Filled Interposer with Top-Side RDLs
217(2)
8.3.12 Fabrication of the Interposer with Bottom-Side RDLs
219(1)
8.3.13 Passive Electrical Characterization of the Interposer
219(2)
8.3.14 Final Assembly
221(3)
8.3.15 Summary and Recommendations
224(1)
8.4 TSV Interposer with Chips on Both Sides
225(18)
8.4.1 The Structure
225(1)
8.4.2 Thermal Analysis-Material Properties
226(1)
8.4.3 Thermal Analysis-Boundary Conditions
226(1)
8.4.4 Thermal Analysis-Result and Discussions
227(3)
8.4.5 Thermomechanical Analysis-Material Properties
230(1)
8.4.6 Thermomechanical Analysis-Boundary Conditions
230(1)
8.4.7 Thermomechanical Analysis-Results and Discussions
230(3)
8.4.8 Interposer Fabrication
233(2)
8.4.9 Microbump Wafer Bumping
235(2)
8.4.10 Final Assembly
237(4)
8.4.11 Summary and Recommendations
241(2)
8.5 Low-Cost TSH Interposer for 3D IC Integration
243(15)
8.5.1 The New Design
243(1)
8.5.2 Electrical Simulation
244(2)
8.5.3 Test Vehicle
246(1)
8.5.4 Top Chip with UBM/Pad and Cu Pillar
247(2)
8.5.5 Bottom Chip with UBM/Pad/Solder
249(1)
8.5.6 TSH Interposer Fabrication
249(1)
8.5.7 Final Assembly
250(3)
8.5.8 Reliability Assessments
253(4)
8.5.9 Summary and Recommendations
257(1)
8.6 References
258(3)
9 Thermal Management of 2.5D/3D IC Integration 261(30)
9.1 Introduction
261(1)
9.2 Design Philosophy
261(1)
9.3 The New Design
262(1)
9.4 Equivalent Model for Thermal Analysis
263(1)
9.5 Interposer with Chip/Heat Spreader on Its Top Side and Chip on Its Bottom Side
264(3)
9.5.1 The Structure
264(1)
9.5.2 Material Properties
264(1)
9.5.3 Boundary Conditions
264(2)
9.5.4 Simulation Results
266(1)
9.6 Interposer with Chip/Heat Spreader on Its Top Side and Chip/ Heat Slug on Its Bottom Side
267(2)
9.6.1 The Structure and Boundary Conditions
267(1)
9.6.2 Simulation Results
268(1)
9.7 Interposer with Four Chips on Its Top Side with Heat Spreader
269(4)
9.7.1 The Structure
269(1)
9.7.2 Boundary Conditions
269(1)
9.7.3 Simulation Results
270(1)
9.7.4 Summary and Recommendations
271(2)
9.8 Thermal Performance between 2.5D and 3D IC Integrations
273(5)
9.8.1 The Structures
273(1)
9.8.2 The Finite Element Models
274(1)
9.8.3 Material Properties and Boundary Conditions
274(2)
9.8.4 Simulation Results-Low-Power Applications
276(1)
9.8.5 Simulation Results-High-Power Applications
276(2)
9.8.6 Summary and Recommendations
278(1)
9.9 Thermal Management System with TSV Interposers with Embedded Microchannels
278(11)
9.9.1 The Structure
278(1)
9.9.2 Adaptor
278(2)
9.9.3 Heat Exchanger
280(1)
9.9.4 Carriers
280(2)
9.9.5 System Integration
282(1)
9.9.6 Theoretical Analysis of the Pressure Drop
283(1)
9.9.7 Experimental Process
284(1)
9.9.8 Results and Discussions
285(3)
9.9.9 Summary and Recommendations
288(1)
9.10 References
289(2)
10 Embedded 3D Hybrid Integration 291(48)
10.1 Introduction
291(1)
10.2 Trends of Optoelectronic Products
291(2)
10.3 The Old Design-High-Frequency Data Link on PCB Using Optical Waveguides
293(12)
10.3.1 Polymer Optical Waveguide
293(2)
10.3.2 Simulations-Optical Coupling Models
295(6)
10.3.3 Simulations-System Link Design
301(1)
10.3.4 Assembly of the OECB
302(1)
10.3.5 Measurement Results of the OECB
303(2)
10.3.6 Summary and Recommendations
305(1)
10.4 The Old Design-Embedded Board-Level Optical Interconnects
305(12)
10.4.1 Fabrication of Polymer Waveguide
305(1)
10.4.2 Fabrication of the 45° Micro-Mirror
306(6)
10.4.3 Assembly Process of the OECB
312(2)
10.4.4 Fabrication Process of Vertical-Optical Channel
314(1)
10.4.5 Final Assembly
314(1)
10.4.6 Summary and Recommendations
315(2)
10.5 The New Designs
317(1)
10.6 An Embedded 3D Hybrid Integration Design Example
318(8)
10.6.1 Optical Design, Analysis, and Results
318(2)
10.6.2 Thermal Design, Analysis, and Results
320(2)
10.6.3 Mechanical Design, Analysis, and Results
322(2)
10.6.4 Summary and Recommendations
324(2)
10.7 Semi-Embedded TSV Interposer with Stress Relief Gap
326(9)
10.7.1 Design Philosophy
326(1)
10.7.2 Problem Definition
327(1)
10.7.3 Semi-Embedded TSV Interposer Subjected to Operating Condition
327(5)
10.7.4 Semi-Embedded TSV Interposer Subjected to an Environmental Condition
332(1)
10.7.5 Summary and Recommendations
333(2)
10.8 References
335(4)
11 3D LED and IC Integration 339(44)
11.1 Introduction
339(1)
11.2 Status and Outlook of Haitz's Law
339(3)
11.3 LED Has Come a Long Way!
342(2)
11.4 Four Key Segments of LED Products
344(4)
11.4.1 Substrates for LED Epitaxial Deposition
344(1)
11.4.2 LED Device Fabrication
345(1)
11.4.3 Packaging Assembly and Test of LED
345(1)
11.4.4 LED Final Product Assembly
345(1)
11.4.5 Outlook of LED Products
346(2)
11.5 3D LED and IC Integration
348(9)
11.5.1 HP FCLED and Thin-Film FCLED
348(1)
11.5.2 3D LED and IC Integration Packages
349(2)
11.5.3 Manufacturing Process of 3D LED and IC Integration
351(5)
11.5.4 Summary and Recommendations
356(1)
11.6 2.5D IC and LED Integration
357(12)
11.6.1 LED Packaging Using Si-Substrate with Cavities and Cu-Filled TSVs
358(3)
11.6.2 Si-Substrate with Cavity and TSVs for LED Packaging
361(4)
11.6.3 LED Wafer-Level Packaging
365(4)
11.6.4 Summary and Recommendation
369(1)
11.7 Thermal Management of 3D LED and IC Integration
369(10)
11.7.1 The New Designs
372(1)
11.7.2 3D IC and LED Integration: A Design Example
372(1)
11.7.3 Boundary-Value Problem
372(1)
11.7.4 Simulation Results (Channel Height = 700 µm)
373(4)
11.7.5 Simulation Results (Channel Height = 350 µm)
377(1)
11.7.6 Summary and Recommendations
377(2)
11.8 References
379(4)
12 3D MEMS and IC Integration 383(34)
12.1 Introduction
383(1)
12.2 MEMS Packaging
383(2)
12.3 Design of 3D MEMS and IC Integration
385(4)
12.3.1 3D MEMS and IC Integration with Lateral Electrical Feed-Through
385(1)
12.3.2 3D MEMS and IC Integration with Vertical Electrical Feed-Through in ASIC
386(2)
12.3.3 3D MEMS and IC Integration with Vertical Electrical Feed-Through in the Package Cap
388(1)
12.3.4 3D MEMS and IC Integration with MEMS on ASIC with TSVs
388(1)
12.3.5 2.5D/2.25D MEMS and IC Integration
388(1)
12.4 Assembly Process of 3D MEMS and IC Integration
389(5)
12.4.1 3D MEMS and IC Integration with Lateral Electrical Feed-Through
389(3)
12.4.2 3D MEMS and IC Integration with Vertical Electrical Feed-Through in ASIC
392(1)
12.4.3 3D MEMS and IC Integration with Vertical Electrical Feed-Through in Package Cap
392(1)
12.4.4 A Note on Case 10-A Real 3D MEMS and IC Integration
393(1)
12.4.5 Summary and Recommendations
393(1)
12.5 Low-Temperature Bonding of 3D MEMS Packaging with Solders
394(8)
12.5.1 3D IC and MEMS Integration with Different Chip Sizes
394(2)
12.5.2 Cavity and TSVs in Cap Wafer
396(1)
12.5.3 MEMS Chip to ASIC Wafer (C2W) Bonding
397(3)
12.5.4 ASIC Wafer with MEMS Chips to Cap Wafer (W2W) Bonding
400(2)
12.5.5 Summary and Recommendations
402(1)
12.6 Recent Developments in Advanced MEMS Packaging
402(13)
12.6.1 TSVs for Wafer-Level Packaging of RF MEMS Devices
402(2)
12.6.2 Zero-Level Packaging for RF-MEMS Implementing TSVs and Metal Bonding
404(6)
12.6.3 MEMS Package Based on Si-Interposer Wafer with Cu-Filled TSVs
410(1)
12.6.4 Wafer-Scale Packaging for FBAR-Based Oscillators
410(4)
12.6.5 Summary and Recommendations
414(1)
12.7 References
415(2)
13 3D CMOS Image Sensor and IC Integration 417(10)
13.1 Introduction
417(1)
13.2 FI-CIS and BI-CIS
417(2)
13.3 3D CIS and IC Stacking
419(2)
13.3.1 The Structure
419(1)
13.3.2 Fabrication of the CIS Pixel Wafer and Logic IC Wafer
420(1)
13.4 3D CIS and IC Integration
421(4)
13.4.1 The Structure
421(1)
13.4.2 Fabrication Process Flow of the Coprocessor Wafer
421(1)
13.4.3 Fabrication Process Flow Of The Cis Wafer
422(2)
13.4.4 Final Assembly
424(1)
13.5 Summary and Recommendations
425(1)
13.6 References
426(1)
14 3D IC Packaging 427(20)
14.1 Introduction
427(1)
14.2 Chip Stacking by Wirebonding
427(1)
14.2.1 Au Wire
427(1)
14.2.2 Cu Wire and Ag Wire
428(1)
14.3 Package-on-Package (PoP)
428(4)
14.3.1 Wirebonding PoP
429(1)
14.3.2 Flip Chip PoP
429(1)
14.3.3 Wirebonding Package on Flip Chip Package
429(1)
14.3.4 PoP in iPhone 5s
429(3)
14.4 Wafer-Level Packaging
432(2)
14.4.1 Fan-In WLP
432(2)
14.4.2 3D Chip-to-Chip WLP
434(1)
14.5 Fan-Out eWLP
434(6)
14.5.1 Fan-Out eWLP
435(2)
14.5.2 3D eWLP-Two-Chip Stacking
437(1)
14.5.3 3D eWLP-Chip on eWLP (Face-to-Face)
437(1)
14.5.4 3D eWLP-Chip on eWLP (Face-to-Back)
438(1)
14.5.5 3D eWLP-Package on eWLP
439(1)
14.5.6 3D eWLP-eWLP on eWLP
440(1)
14.6 Embedded Panel-Level Packaging
440(4)
14.6.1 Advantages and Disadvantages
440(1)
14.6.2 Various Chip-Embedding Processes
441(2)
14.6.3 Embedded Chip in SiP Rigid Substrate
443(1)
14.6.4 3D Embedded Chip in SiP Flexible Substrate
443(1)
14.6.5 3D Embedded Stacking Chips in SiP Flexible Substrate
443(1)
14.7 Summary and Recommendations
444(1)
14.8 References
445(2)
Index 447
John H. Lau received his Ph.D. degree in Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also has a B.E. degree in Civil Engineering from National Taiwan University (1970). John is an interconnection technology scientist at Agilent Technologies, Inc. His current interests cover a broad range of electronic and optoelectronic packaging and manufacturing technology. Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, petroleum, nuclear, and defense industries, he has given over 200 workshops, authored and co-authored over 180 peer reviewed technical publications, and is the author and editor of 13 books: Solder Joint Reliability; Handbook of Tape Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects; Handbook of Fine Pitch Surface Mount Technology; Chip On Board Technologies for Multichip Modules; Ball Grid Array Technology; Flip Chip Technologies; Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Electronics Packaging: Design, Materials, Process, and Reliability; Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, and Microvias for Low Cost, High Density Interconnects. John served as one of the associate editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and session chairman, and invited speaker of several IEEE, ASME, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from ASME and IEEE for best papers and outstanding technical achievements, and is an ASME Fellow and an IEEE Fellow. He is listed in American Men and Women of Science and Whos Who in America.
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