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E-raamat: 3D Integration in VLSI Circuits: Implementation Technologies and Applications

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3D Integration in VLSI Circuits: Implementation Technologies and ApplicationsSuurem pilt
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Currently, the term 3D integration includes a wide variety of different integration methods, such as 2.5-dimensional (2.5D) interposer-based integration, 3D integrated circuits (3D ICs), 3D systems-in-package (SiP), 3D heterogeneous integration, and monolithic 3D ICs. The goal of this book is to provide readers with an understanding of the latest challenges and issues in 3D integration. TSVs are not the only technology element needed for 3D integration. There are numerous other key enabling technologies required for 3D integration, and the speed of the development in this emerging field is very rapid. To provide readers with state-of-the-art information on 3D integration research and technology developments, each chapter has been contributed by some of the worlds leading scientists and experts from academia, research institutes, and industry from around the globe.











Covers chip/wafer level 3D integration technology, memory stacking, reconfigurable 3D, and monolithic 3D IC.





Discusses the use of silicon interposer and organic interposer.





Presents architecture, design, and technology implementations for 3D FPGA integration.





Describes oxide bonding, Cu/SiO2 hybrid bonding, adhesive bonding, and solder bonding.





Addresses the issue of thermal dissipation in 3D integration.

Arvustused

"With the increasing cost and power issues associated with continuing along the traditional road of 2D scaling, 3D integration is becoming an essential enabler for performance gains in future VLSI nodes. This book provides an insightful treatment of the challenges and opportunities for intelligently evolving 3D integration into volume manufacturing and the applications that will exploit this exciting technology." David Danovitch, Université de Sherbrooke, Canada

"The chapter authors are the worlds leading scientists and experts in this field and they cover the state-of-the-art topics that the readers really want." James J.-Q. Lu, Rensselaer Polytechnic Institute, USA "With the increasing cost and power issues associated with continuing along the traditional road of 2D scaling, 3D integration is becoming an essential enabler for performance gains in future VLSI nodes. This book provides an insightful treatment of the challenges and opportunities for intelligently evolving 3D integration into volume manufacturing and the applications that will exploit this exciting technology." David Danovitch, Université de Sherbrooke, Canada

"The chapter authors are the worlds leading scientists and experts in this field and they cover the state-of-the-art topics that the readers really want." James J.-Q. Lu, Rensselaer Polytechnic Institute, USA

Preface vii
Series Editor xi
Editor xiii
Contributors xv
1 Three-Dimensional Integration: Technology and Design 1(14)
P. Franzon
1.1 Introduction
1(1)
1.2 Three-Dimensional Integrated Circuit Technology Set
2(3)
1.3 Three-Dimensional Drivers
5(1)
1.4 Miniaturization
5(1)
1.5 Cost Reduction
6(1)
1.6 Heterogeneous Integration
7(1)
1.7 Performance Enhancement
8(2)
1.8 Power Efficiency
10(2)
1.9 Conclusion
12(1)
References
12(3)
2 Three-Dimensional System-in-Package for Application-Specific Integrated Circuit and Three-Dimensional Dynamic Random-Access Memory Integration 15(26)
Li Li
2.1 Three-Dimensional SiP Introduction
15(2)
2.2 Enabling Technologies for 3D SiP
17(8)
2.2.1 Three-Dimensional Stackable Memory
17(2)
2.2.2 High-Density Interposer
19(4)
2.2.2.1 Silicon Interposer
19(2)
2.2.2.2 Organic Interposer
21(2)
2.2.3 Microbump Interconnect
23(2)
2.3 3D SiP for Application-Specific Integrated Circuits and High Bandwidth Memory Integration
25(4)
2.3.1 Organic Interposer Design
26(1)
2.3.2 Simulation and Results
27(2)
2.4 Three-Dimensional SiP Assembly
29(3)
2.5 Test and Characterization
32(1)
2.6 Reliability Challenge
33(4)
2.7 Summary
37(1)
References
38(3)
3 A New Class of High-Capacity, Resource-Rich Field-Programmable Gate Arrays Enabled by Three-Dimensional Integration Chip-Stacked Silicon Interconnect Technology 41(30)
Suresh Ramalingam
Henley Liu
Myongseob Kim
Boon Ang
Woon-Seong Kwon
Tom Lee
Susan Wu
Jonathan Chang
Ephrem Wu
Xin Wu
Liam Madden
3.1 Introduction
42(1)
3.2 Architecture, Design, and Product Enablement
43(12)
3.2.1 Key Challenges
44(1)
3.2.1.1 Limited Connectivity and Bandwidth
44(1)
3.2.1.2 Excessive Latency
44(1)
3.2.1.3 Power Penalty
44(1)
3.2.2 Xilinx-Stacked Silicon Interconnect Technology
45(9)
3.2.2.1 Creating Field-Programmable Gate Array Die Slices with Microbumps for Stacked Silicon Integration
46(1)
3.2.2.2 Silicon Interposer with Through-Silicon Vias
47(1)
3.2.2.3 Three-Dimensional Integration Chip Analysis Methodology Enablement with Simulation Program with Integrated Circuit Emphasis Simulators
48(2)
3.2.2.4 Silicon Interposer Signal Integrity
50(4)
3.2.3 Three-Dimensional Integration Chip Resource-Rich Field-Programmable Gate Arrays Product Offerings
54(1)
3.3 Stacked Silicon Technology Development and Package Reliability
55(12)
3.3.1 Key-Enabling Technologies
55(4)
3.3.1.1 Silicon-Grinding Quality Optimization
57(1)
3.3.1.2 Wafer Edge and Bevel-Cleaning Optimization
57(1)
3.3.1.3 Silicon-Footing Improvement
58(1)
3.3.2 Three-Dimensional Integration Chip Development Test Vehicles
59(6)
3.3.2.1 28 nm Test Vehicle-Driven Process and Reliability Improvements
60(1)
3.3.2.2 Improvements to 20 nm Test Vehicle
61(2)
3.3.2.3 Board-Level Reliability Test Vehicle and Results
63(2)
3.3.3 Three-Dimensional Integration Chip Reliability Look-Ahead Assessments
65(22)
3.3.3.1 Continuous Process Yield Improvements
66(1)
3.4 Potential Three-Dimensional Integration Chip Future Challenges
67(1)
Acknowledgment
68(1)
References
68(3)
4 Challenges in 3D Integration 71(14)
M. Koyanagi
T. Fukushima
T. Tanaka
4.1 Introduction
71(1)
4.2 Past Challenges in Three-Dimensional Integration
72(1)
4.3 Challenges in Three-Dimensional System Integration
73(3)
4.4 Challenges in Three-Dimensional Heterogeneous Integration
76(3)
4.5 Challenges toward Future Three-Dimensional Integration
79(2)
4.6 Summary
81(1)
References
81(4)
5 Wafer-Level Three-Dimensional Integration Using Bumpless Interconnects and Ultrathinning 85(32)
Takayuki Ohba
5.1 Introduction
86(1)
5.2 Co-Engineering by 3D and 2D
87(3)
5.2.1 Delay of Three-Dimensional Integration Technology
87(1)
5.2.2 Economic and Technical Issues for Lithography
87(1)
5.2.3 Co-Engineering Using Three Dimensional for Next Generation of Manufacturing
88(2)
5.3 Bumpless Interconnecting and Wafer-Level Three-Dimensional Integration
90(2)
5.3.1 Overview of Bumpless Interconnects
90(1)
5.3.2 Thickness of Wafer and Ultrathinning
91(1)
5.4 Details of Wafer-Level Three-Dimensional Process
92(6)
5.4.1 Thinning Module
92(1)
5.4.2 Stacking Module
93(1)
5.4.3 Through-Silicon Via Module
94(3)
5.4.4 Packaging Module (Singulation/Packaging Module)
97(1)
5.5 Device Characteristics after Ultrathinning
98(5)
5.5.1 Retention Time Change of Dynamic Random-Access Memory after Thinning
98(1)
5.5.2 Ultrathinning and Estimation of Critical Thickness
99(2)
5.5.3 Cu-Diffusion Phenomenon at Ground Surface
101(2)
5.6 Characteristics of Low-Aspect Ratio Through-Silicon Via Interconnects
103(3)
5.6.1 Step Coverage and Cu Diffusion
103(1)
5.6.2 Stresses in Cu Through-Silicon Vias
104(2)
5.6.3 Electrical Characteristics
106(1)
5.7 Thermal Resistance of Bumpless Interconnects and Thin Wafers
106(4)
5.8 Concurrent Manufacturing Using WOW
110(4)
5.8.1 Enhancement of Memory Capacity
110(1)
5.8.2 Yield in Wafer Stacking
111(1)
5.8.3 Benefits of Co-Engineering
112(2)
5.9 Summary and Conclusions
114(1)
References
114(3)
6 Three-Dimensional Integration Stacking Technologies for High-Volume Manufacturing by Use of Wafer-Level Oxide-Bonding Integration 117(28)
Spyridon Skordas
Katsuyuki Sakuma
Kevin Winstel
Chandrasekharan Kothandaraman
6.1 Introduction
118(3)
6.1.1 Rationale for Three-Dimensional Integration
118(2)
6.1.2 Rationale for Wafer-Bonding Technology
120(1)
6.1.3 Description of Work
120(1)
6.2 Chip-Level Three-Dimensional Integration with 22 nm Complementary Metal-Oxide-Semiconductor Technology
121(4)
6.3 Wafer-Bonding Technology for Three-Dimensional Integration Stacking
125(4)
6.3.1 Metal-Metal Bonding
126(1)
6.3.2 Hybrid Bonding
127(1)
6.3.3 Oxide Bonding
128(1)
6.4 Oxide-Bonding Technology for Embedded Dynamic Random Access Memory Stacking
129(6)
6.4.1 Oxide-Bonding Layer Preparation
129(2)
6.4.2 Wafer-Level Three-Dimensional Integration with Oxide Bonding
131(4)
6.5 Key Electrical Metrics Performance Results for Embedded Dynamic Random Access Memory Stacking
135(5)
6.6 Summary
140(1)
Acknowledgments
141(1)
References
141(4)
7 Toward Three-Dimensional High Density 145(40)
S. Cheramy
A. Jouve
C. Fenouillet-Beranger
P. Vivet
L. Di Cioccio
7.1 Introduction
146(1)
7.2 Cu/SiO2 Hybrid Bonding
147(15)
7.2.1 Cu/SiO2 Hybrid Bonding Principle
147(1)
7.2.2 Technical Challenges Linked to Hybrid Bonding
148(7)
7.2.2.1 Surface Preparation
148(1)
7.2.2.2 Bonding Interface Characterization
149(3)
7.2.2.3 Bonding Energy Evolution with Temperature
152(1)
7.2.2.4 Copper Modification with Temperature
152(2)
7.2.2.5 Wafer Alignment Consideration
154(1)
7.2.2.6 Investigation on Copper Diffusion
154(1)
7.2.2.7 Pad Dimension Reduction
155(1)
7.2.3 Electrical Performances Evaluation of Hybrid Bonding
155(4)
7.2.3.1 Electrical Structures Presentation and Performances
155(2)
7.2.3.2 Environmental Reliability Study
157(1)
7.2.3.3 Electromigration
158(1)
7.2.4 Hybrid Bonding Maturity Increase: Moving toward Production
159(1)
7.2.5 Specificity of the Die-to-Wafer Process Variation
160(1)
7.2.6 Die-to-Wafer Process Throughput Increase with Self-Assembly
161(1)
7.3 3D Sequential: 3D Very-Large-Scale-Integration CoolCube™
162(10)
7.3.1 3D Sequential: Principle
163(1)
7.3.2 3D Sequential: State of the Art
164(1)
7.3.3 3D Sequential: Integration Process Flow and Low-Temperature Top FETs
165(2)
7.3.4 3D Sequential: Intermediate Back-End-of-Line
167(2)
7.3.5 3D Sequential: 300 mm Electrical Demonstration
169(3)
7.4 3D Technologies Comparative Thermal Analysis
172(7)
7.4.1 3D Technology Parameters for Thermal Comparison
172(3)
7.4.2 Comparative Study Thermal Results
175(2)
7.4.2.1 For Hot-Spot Dissipation Scenarios
176(1)
7.4.2.2 For Uniformly Distributed Power Dissipation Scenarios
177(1)
7.4.3 Thermal Comparison Conclusion
177(2)
7.5 General Conclusion
179(1)
References
179(6)
8 Novel Platforms and Applications Using Three-Dimensional and Heterogeneous Integration Technologies 185(26)
Kuan-Neng Chen
Ting-Yang Yu
Yu-Chen Hu
Cheng-Hsien Lu
8.1 Introduction
186(1)
8.2 Stacked Terahertz Optical Component
186(8)
8.2.1 THz Wave Applications
186(1)
8.2.2 Issues of Common THz Polarizers
187(1)
8.2.3 Fundamentals and Fabrication Methods
188(2)
8.2.3.1 Structure Design of THz Polarizer
188(1)
8.2.3.2 Fabrication Methods and Low-Temperature Eutectic Liquid Bonding
189(1)
8.2.4 Performance of Staked THz Polarizer
190(3)
8.2.4.1 Bonding and Etching Qualities
190(1)
8.2.4.2 High Transmittance THz Polarizer
191(1)
8.2.4.3 Broadband THz Polarizer
192(1)
8.2.5 Comparison between Common and Stacked THz Polarizers
193(1)
8.3 Pressure-Sensing System
194(6)
8.3.1 Pressure-Sensing Platform
195(1)
8.3.2 Pressure Sensor
196(1)
8.3.3 Micropin-Fin Heat Sink Interposer
196(2)
8.3.4 Integration of Micropin-Fin Heat Sink Interposer and Chips with Double-Self-Assembly Approach
198(1)
8.3.5 Achievements and Outlook
199(1)
8.4 Neurosensing Systems
200(8)
8.4.1 Fabrication, Scheme, and Reliability of Neural Sensing Biosensor
201(2)
8.4.1.1 Three-Dimensional System-in-Packaging Neural Sensing Biosensor
201(1)
8.4.1.2 Chip-Level Heterogeneous Integration Scheme
201(1)
8.4.1.3 Electroplating Solution Improvement
201(2)
8.4.1.4 Electrical Reliability Tests
203(1)
8.4.2 2.5D-Silicon Interposer Neural Sensing Biosensor
203(2)
8.4.2.1 Fabrication of Silicon Interposer and Through-Silicon Via-Embedded µ-Probe
204(1)
8.4.2.2 Electrical Reliability Test
204(1)
8.4.3 2.5D-Flexible Interposer Neural Sensing Biosensor
205(2)
8.4.3.1 Fabrication of Flexible Interposer
205(1)
8.4.3.2 Novel Flexible Bonding Approach
206(1)
8.4.3.3 Electrical Reliability Test of Novel Thin Film-Bonding Approaches
206(1)
8.4.4 Demonstration
207(1)
References
208(3)
Index 211
Katsuyuki Sakuma is a research staff member at the IBM T. J. Watson Research Center. Currently, he is also a Visiting Professor at the Department of Biomedical Engineering, Tohoku University, Japan. He has over 19 years of experience of researching 3D integration technologies and performing various semiconductor packaging research and development projects.



His research interests include 3D integration technologies, bonding technologies, and advanced packaging. He has published more than 85 peer-reviewed journal papers and conference proceeding papers, including three book chapters in the semiconductor and electronic packaging area. He also holds over 35 issued or pending U.S. and international patents. He has been recognized with the IBM Eleventh Invention Achievement Award in 2017 and an Outstanding Technical Achievement Award (OTAA) in 2015 for his contribution and leadership in the area of 3D integration technology development. He was also given the 2018 Exceptional Technical Achievement Award from IEEE Electronics Packaging Society and the 2017 Alumni Achievement Award from his Alma Mater, the School of Engineering at Tohoku University, for his contribution to 3D chip stack technology development in the electronics packaging industry. He was co-recipient of the IEEE CPMT Japan Society Best Presentation Award in 2012, and the IMAPS "Best of Track" Outstanding Paper Award in 2015.



Dr. Sakuma received his B.S. and M.S. degrees from Tohoku University, and the Ph.D. degree from Waseda University, Japan. He is currently serving as an Associate Editor for IEEE Transactions on Components, Packaging and Manufacturing Technology (CPMT). He served as an Associate Editor of the Institute of Electronics, Information and Communication Engineers (IEICE, Japan) from 2003 until 2005. He has served as committee member of the IEEE ECTC Interconnections sub-committee since 2012, for the IEEE International Conference on 3D System Integration (IEEE 3DIC) since 2016, and for the IEEE International Reliability Physics Symposium (IEEE IRPS) since 2017. He has been a senior member of IEEE since 2012.
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