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E-raamat: 3D TCAD Simulation for CMOS Nanoeletronic Devices

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Yi-Ruei Jhan, Yung-Chun Wu

Formaat: PDF+DRM
Ilmumisaeg: 19-Jun-2017
Kirjastus: Springer Verlag, Singapore
Keel: eng
ISBN-13: 9789811030666

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Formaat: PDF+DRM
Ilmumisaeg: 19-Jun-2017
Kirjastus: Springer Verlag, Singapore
Keel: eng
ISBN-13: 9789811030666

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This book demonstrates how to use the Synopsys Sentaurus TCAD 2014 version for the design and simulation of 3D CMOS (complementary metal–oxide–semiconductor) semiconductor nanoelectronic devices, while also providing selected source codes (Technology Computer-Aided Design, TCAD). Instead of the built-in examples of Sentaurus TCAD 2014, the practical cases presented here, based on years of teaching and research experience, are used to interpret and analyze simulation results of the physical and electrical properties of designed 3D CMOSFET (metal–oxide–semiconductor field-effect transistor) nanoelectronic devices.

The book also addresses in detail the fundamental theory of advanced semiconductor device design for the further simulation and analysis of electric and physical properties of semiconductor devices. The design and simulation technologies for nano-semiconductor devices explored here are more practical in nature and representative of the semiconductor industry, and as such can promote the development of pioneering semiconductor devices, semiconductor device physics, and more practically-oriented approaches to teaching and learning semiconductor engineering.

The book can be used for graduate and senior undergraduate students alike, while also offering a reference guide for engineers and experts in the semiconductor industry. Readers are expected to have some preliminary knowledge of the field.

1 Introduction of Synopsys Sentaurus TCAD Simulation

(18)

1.1 Introduction

(1)

1.2 Introduction of Moore's Law and FinFET

(3)

1.3 Sentaurus Window Environment and Workbench for TCAD Task Management

(3)

1.4 Synopsys Sentaurus TCAD Software and Working Environment

(6)

1.5 Simulation Project View on Sentaurus Workbench (SWB)

(1)

1.6 Sentaurus Visual

(2)

1.7 Calibration and Services

(3)

References

(2)

2 2D MOSFET Simulation

(72)

2.1 Complementary MOS (CMOS) Technology

(4)

2.2 [ Example 2.1] 2D n-Type MOSFET with Id--Vg Characteristics Simulation

(28)

2.3 [ Example 2.2] 2D n-Type MOSFET with Id--Vd Characteristics Simulation

(9)

2.4 [ Example 2.3] 2D p-Type MOSFET with Id--Vg Characteristics Simulation

(9)

2.5 [ Example 2.4] 2D p-Type MOSFET with Id--Vg Characteristics Simulation

(10)

2.6 [ Example 2.5] 2D n-Type MOSFET with LDD (Lightly Doped Drain) Simulation

(11)

2.7 Summary

(1)

References

(1)

3 3D FinFET with Lg = 15 nm and Lg = 10 nm Simulation

(94)

3.1 Introduction of FinFET

(4)

3.2 Design Considerations of Threshold Voltage (Vth), Leakage Current (Ioff), and Power Consumption (Power)

(3)

3.3 Design Considerations of High-k Dielectric Materials and Metal Gate

(3)

3.4 Design Consideration of Device Gate and TCAD Design Guideline

101

(3)

3.5 FinFET 3D Simulation

104

(81)

3.5.1 Establishment of FinFET Structure

104

(1)

3.5.2 Physical Property Analysis

105

(78)

References

183

(2)

4 Inverter and SRAM of FinFET with Lg = 15 nm Simulation

185

(26)

4.1 Voltage Transfer Curve of Inverter

185

(2)

4.2 Speed of CMOS Inverter---Importance of Ion

187

(1)

4.3 CMOS Id--Vg Matching Diagram for High-Performance Transistors

188

(1)

4.4 [ Example 4.1] Inverter of 3D FinFET with Lg = 15 nm

189

(6)

4.5 TCAD Simulation of Static Random-Access Memory (SRAM)

195

(1)

4.6 SRAM Operation

196

(4)

4.7 [ Example 4.2] Simulation of SRAM of 3D FinFET with Lg = 15 nm

200

(11)

References

210

(1)

5 Gate-All-Around (GAA) NWFET with L8 = 10 nm Simulation

211

(26)

5.1 Introduction of Gate-All-Around Nanowire FET (GAA NWFET)

211

(3)

5.2 [ Example 5.1] 3D IM n-Type GAA NWFET

214

(8)

5.3 [ Example 5.2] 3D IM p-Type GAA NWFET

222

(5)

5.4 [ Example 5.3] 3D Cylindrical IM n-Type GAA NWFET

227

(10)

References

236

(1)

6 Junctionless FET with Lg = 10 nm Simulation

237

(20)

6.1 Foreword

237

(1)

6.2 Short-Channel Effect (SCE) of CMOS Device

238

(1)

6.3 JL---FET Operating Mechanism

239

(3)

6.4 [ Example 6.1] n-Type JL---FET with Lg = 10 nm

242

(3)

6.5 [ Example 6.2] p-Type JL---FET with Lg = 10 nm

245

(12)

References

255

(2)

7 Steep Slope Tunnel FET Simulation

257

(22)

7.1 Problems Facing Conventional MOSFET

257

(1)

7.2 Operating Mechanism of Tunnel FET (TFET)

258

(3)

7.3 Example 7.1 (Design and Simulation of 3D n-Type TFET)

261

(7)

7.4 Example 7.2 (3D n-Type TFET of Different Drain Doping Concentrations)

268

(4)

7.5 Example 7.3 (3D n-Type TFET with Asymmetrical Gate)

272

(6)

7.5.1 Descriptions of Motivation and Principle

272

(6)

7.6 Summary of This
Chapter

278

(1)

References

278

(1)

8 Extremely Scaled Si and Ge to Lg = 3-nm FinFETs and Lg = 1-nm Ultra-Thin Body Junctionless FET Simulation

279

(26)

8.1 Foreword

279

(2)

8.1.1 Challenges of Sub-10-nm Technology Node

280

(1)

8.1.2 Material Selection for Sub-10-nm Technology Node

280

(1)

8.2 Design Guideline of Sub-20-nm to 9-nm Gate Length Si FinFET of Wine-Bottle Channel

281

(2)

8.2.1 Device Structure and Sub-20-nm FinFET Experimental Data

281

(1)

8.2.2 Simulation Results and Discussion

281

(2)

8.3 Study of Silicon Lg = 3-nm Bulk IM, AC, and JL FinFET

283

(8)

8.4 Study of Germanium Lg = 3-nm Bulk FinFET

291

(6)

8.5 Study of Silicon and Germanium UTB-JL---FET with Ultra-Short Gate Length = 1 and 3 nm

297

(8)

References

302

(3)

Appendix: Synopsys Sentaurus TCAD 2014 Version Software Installation and Environmental Settings

305

Dr. Yung-Chun Wu received his B.S. degree in Physics from National Central University in 1996, his M.S. degree in Physics from National Taiwan University in 1998, and his Ph.D. from National Chiao Tung University, Taiwan, in 2005. From 1998 to 2002, he was an assistant researcher at National Nano Device Laboratories, Hsinchu, Taiwan, where he was primarily engaged in research on single electron transistor and electron beam lithography technology. In 2006, he joined the Department of Engineering and System Science, National Tsing-Hua University, Hsinchu, Taiwan, where he is currently working as an associate professor. He teaches 3D CMOS semiconductor nanoelectronic devices by TCAD simulation course for seven years. His research interests include nanoelectronic devices and 3D TCAD simulation, flash memory devices, and solar cells. He has published 56 international SCI papers on nanoelectronic devices.

Yi-Ruei Jhan received the B.S. degree in Physics from National Dong Hwa University in 2010, M. S. degree in Engineering and System Science from National Tsing Hua University in 2012, and Ph.D. degree in Engineering and System Science from National Tsing Hua University in 2015. In 2016, he joined the Research and Development department of Taiwan Semiconductor Manufacturing Company (TSMC) after his graduation. His research interests include Nanoelectronic MOSFET devices, TCAD simulation and Nonvolatile memory devices. He is author of book: 3D TCAD Simulation for CMOS Nanoeletronic Devices.

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