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E-raamat: Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling: From the Clock Path to the Data Path

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  • Formaat: EPUB+DRM
  • Ilmumisaeg: 27-Feb-2020
  • Kirjastus: Springer Nature Switzerland AG
  • Keel: eng
  • ISBN-13: 9783030387969
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Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling: From the Clock Path to the Data PathSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 27-Feb-2020
  • Kirjastus: Springer Nature Switzerland AG
  • Keel: eng
  • ISBN-13: 9783030387969
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This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling.  Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical).  Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications.  All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.

1 Introduction
1(16)
1.1 Trends in the Semiconductor Industry
2(2)
1.2 Energy Considerations in Power-Limited and Battery-Powered Systems
4(5)
1.3 Wide Power-Performance Tradeoff and System Requirements
9(3)
1.3.1 Importance of Wide Power-Performance Tradeoff in Duty-Cycled and Always-on Systems
9(2)
1.3.2 Wide Voltage Scaling
11(1)
1.4 Challenges in Wide Voltage Scaling and Motivation
12(2)
1.5 Book Outline
14(1)
References
14(3)
2 Reconfigurable Microarchitecures Down to Pipestage and Memory Bank Level
17(38)
2.1 Pipestage as Basic Building Block of Synchronous Microarchitectures
18(6)
2.1.1 Background on Pipeline Stages and Timing Constraints
18(3)
2.1.2 Pipelining for Microarchitecture Speed-Up
21(3)
2.2 Elementary Microarchitectures
24(2)
2.3 Impact of Logic Depth on Energy
26(2)
2.4 Dynamically Adaptable Pipelines
28(8)
2.4.1 Wide Dynamic Voltage Frequency Scaling
28(2)
2.4.2 Dynamically Adaptable Pipeline
30(5)
2.4.3 Run-Time Pipeline Adaptation via Augmented DVFS Look-Up Table
35(1)
2.5 Microprocessor Microarchitectures: Opportunities and Challenges Under Reconfiguration
36(4)
2.5.1 Wide DVFS in Microprocessors and Considerations at the Application Level
36(1)
2.5.2 Control Flow and Hazards in Microprocessor Microarchitectures with Different Pipedepths
37(2)
2.5.3 Limitations of Re-pipelining in Existing Microprocessor Architectures
39(1)
2.6 Enabling Microarchitectural Reconfiguration in Microprocessors
40(2)
2.7 Dynamically Adaptable Time-Interleaved Microprocessors
42(5)
2.8 Static Random Access Memory (SRAM)
47(3)
2.9 Methods for SRAM Speed-Up via Reconfigurable Array Organization
50(1)
2.10 Conclusion
51(1)
References
51(4)
3 Automated Design Flows and Run-Time Optimization for Reconfigurable Microarchitecures
55(38)
3.1 Prior Art in Reconfigurable Microarchitectures
56(2)
3.2 Overview of Systematic Methodologies and Design Flows for Microarchitectural Reconfiguration
58(1)
3.3 Automated Design Flow for Pipeline-Level Reconfiguration: Re-pipelining and Retiming (Steps 1-2)
59(4)
3.3.1 Re-pipelining (Step 1)
59(2)
3.3.2 Retiming (Step 2)
61(2)
3.4 Automated Design Flow for Pipeline-Level Reconfiguration: Register Identification (Step 3, Phase I)
63(3)
3.4.1 Netlist to Skeleton Graph (Step 3.1, Phase I)
63(2)
3.4.2 Weighted Skeleton Graph (Step 3.2, Phase I)
65(1)
3.5 Automated Design Flow for Pipeline-Level Reconfiguration: Register Identification in Linear Pipelines (Step 3, Phase II)
66(1)
3.6 Automated Design Flow for Pipeline-Level Reconfiguration: Register Identification in Non-linear Pipelines (Step 3, Phase II).
67(8)
3.6.1 Graph Feedforward Cutsets and Properties
68(2)
3.6.2 Cutset Identification (Step 3.3B)
70(3)
3.6.3 Cutset-to-Pipeline Mapping (Step 3.3C)
73(2)
3.7 Automated Design Flow for Pipeline-Level Reconfiguration: Bypassable Registers Choice (Step 3, Phase III)
75(1)
3.8 Automated Design Flow for Pipeline-Level Reconfiguration: Bypassable Register Replacement (Step 4)
76(2)
3.9 Automated Design Flow Extension to Thread-Level Time-Interleaved Reconfiguration
78(2)
3.10 SRAM Reconfiguration at the Bank Level
80(9)
3.10.1 Design Considerations on Memory Reconfiguration
80(1)
3.10.2 Background on Low-Power and Reconfigurable Memories
81(4)
3.10.3 Row Aggregation Technique and Reconfiguration for Selective Performance Enhancement Beyond Nominal Voltage
85(1)
3.10.4 Embedding Reconfigurable Row Aggregation Through Minor Modifications of Existing Compiled Memories
85(4)
3.11 Conclusion
89(1)
References
90(3)
4 Case Studies of Reconfigurable Microarchitectures: Accelerators, Microprocessors, and Memories
93(22)
4.1 Fast Fourier Transform (FFT) Accelerator
94(11)
4.1.1 Microarchitecture and Design of Its Dynamically Adaptable Pipeline Counterpart
94(2)
4.1.2 Measurement Results on a Single Die
96(2)
4.1.3 Impact of Variations and Comparison of Measurement Results Across Multiple Dice
98(1)
4.1.4 Overhead Due to Microarchitecture Reconfiguration
99(6)
4.2 Finite Impulse Response Filter (FIR) and Fixed-Point Multiplier
105(2)
4.3 Reconfigurable Thread-Level in ARM Cortex Microcontroller and SRAM Row Aggregation
107(5)
4.3.1 Reconfigurable Memory with Selective Row Aggregation
109(2)
4.3.2 ARM Cortex-MO Microcontroller
111(1)
4.4 Conclusion
112(1)
References
113(2)
5 Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study
115(30)
5.1 Impact of Clock Network Topology on Clock Skew, Performance, and Hold Margin under Wide Voltage Scaling
116(6)
5.1.1 Impact of Clock Skew on Performance, Robustness Against Hold Violations, and Energy Efficiency
116(2)
5.1.2 Impact of Supply Voltage on Clock Network Optimization and Clock Skew in Conventional Static Clock Networks
118(3)
5.1.3 Prior Art in Clock Networks for Low- or Wide-Voltage Operation
121(1)
5.2 Reconfigurable Clock Networks: Principles and Fundamentals
122(2)
5.3 Bypassable Repeaters and Other Clock Cells
124(4)
5.4 Gate-Boostable Clock Root Repeater
128(1)
5.5 Automated Design Flows for Reconfigurable Clock Networks and Integration with DVFS
129(5)
5.5.1 Automated Clock Tree Design and Level Balance Principle
129(3)
5.5.2 Optimal Configuration Selection and Integration with DVFS
132(2)
5.6 Case Study: Reconfigurable Clock Network in FFT Accelerator
134(8)
5.6.1 Testchip Design
134(4)
5.6.2 Clock Skew Measurement Results
138(3)
5.6.3 Improvements in Performance, Robustness, and Energy Offered by Reconfigurable Clock Networks
141(1)
5.7 Conclusion
142(1)
References
143(2)
6 Conclusions
145(4)
References
148(1)
Appendix 149(14)
Index 163
Saurabh Jain received the bachelors and masters degrees from Indian Institute of Technology, Kanpur, India, in 2012 and 2013 respectively, the Ph.D. degree from National University of Singapore, Singapore, in 2018. After his Ph.D. he worked as a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore. Currently he is working as a research scientist at the processor architecture research lab (PARL) at Intel Labs, Bangalore.





His research interest includes development of reconfigurable architectures for widely voltage-scalable memory and logic and general purpose compute-in-memory.





Longyang Lin received the dual bachelor's degrees from Shenzhen University, Shenzhen, China and Umeå University, Umeå, Sweden, in 2011 and the master's degree from Lund University, Lund, Sweden, in 2013, and the Ph.D. degree from the National University of Singapore, Singapore, in 2018. He is currently a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore.





His research interests include ultra-low power VLSI circuits, self-powered sensor nodes, widely energy-scalable VLSI circuits and general purpose compute-in-memory.





Massimo Alioto received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, and the Bachelor of Music in Jazz Studies from the Conservatory of Music of Bologna in 2007. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007).





He has authored or co-authored more than 280 publications on journals and conference proceedings. He is co-author of four books, including Enabling the Internet of Things - from Circuits to Systems (Springer, 2017), Flip-Flop Design in Nanometer CMOS - from High Speed to Low Energy (Springer, 2015), and Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include self-powered wireless integrated systems, near-threshold circuits for green computing, widely energy- scalable and energy-quality scalable integrated systems, data-driven integrated systems, hardware-level security, and emerging technologies, among the others.





He is the Editor in Chief of the IEEE Transactions on VLSI Systems (2019-2020), and was the Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). In 2009-2010 he was Distinguished Lecturer of theIEEE Circuits and Systems Society, for which he is/was also member of the Board of Governors (2015-2020), and Chair of the VLSI Systems and Applications Technical Committee (2010-2012). In the last five years, he has given 50+ invited talks in top conferences, universities and leading semiconductor companies. His research has been mentioned in more than 60 press releases and popular science articles in the last two years. He served as Guest Editor of several IEEE journal special issues (e.g., TCAS-I, TCAS-II, JETCAS). He also serves or has served as Associate Editor of a number of IEEE and ACM journals. He is/was Technical Program Chair (ISCAS 2023, SOCC, ICECS, NEWCAS, VARI, ICM, PRIME) and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). Currently, he is also in the IEEE Digital Architectures and Systems ISSCC subcommittee, and the IEEE ASSCC technical program committee. Prof. Alioto is an IEEE Fellow.
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