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Advances in Electronic Testing: Challenges and Methodologies is a new type of edited volume in the Frontiers in Electronic Testing book series devoted to recent advances in electronic circuits testing. The book is a comprehensive elaboration on important topics which capture major research and development efforts today. The motivation and inspiration behind this book is to deliver a thorough text that focuses on the evolution of test technology, provides insight about the abiding importance of discussed topics, records todays state of the art and industrial practices and trends, reveals the challenges for emerging testing methodologies, and envisages the future of this journey.



The book consists of eleven edited chapters written by experts in Defect-Oriented Testing, Nanometer Technologies Failures and Testing, Silicon Debug, Delay Testing, High-Speed Test Interfaces, DFT-Oriented Low-Cost Testers, Embedded Cores and System-on-Chip Testing, Memory Testing, Mixed-Signal Testing, RF Testing and Loaded Board Testing. Contributing authors are affiliated with (in alphabetical order) Agilent, ARM, Balearic Islands Univ., IBM, Inovys, Intel, LogicVision, Magma, Mentor Graphics, New Mexico Univ., Sandia National Labs, Synopsys, Teradyne and Texas Instruments.



Advances in Electronic Testing: Challenges and Methodologies is an advanced textbook and reference point for senior undergraduate and graduate students in MSc or PhD tracks, professors and research leaders in the electronic testing domain. It is also for industry design and test engineers and managers seeking a global view and understanding of test technology practices and methodologies and a dense elaboration on test-related issues they face in their development projects.



"There is a definite need for documenting the advances in testing I find the work of this edited volume by Dimitris Gizopoulos and his team of authors to be significant and timely. [ ] the book provides, besidesnovel test methodologies, a collective insight into the emerging aspects of testing. This, I think, is beneficial to practicing engineers and researchers both of whom must stay at the forefront of technology. [ ] This latest addition to the Frontiers Series is destined to serve an important role." From the Foreword by Vishwani D. Agrawal, Consulting Editor, Frontiers in Electronic Testing Book Series.

Arvustused

"There is a definite need for documenting the advances in testing I find the work of this edited volume by Dimitris Gizopoulos and his team of authors to be significant and timely. [ ] the book provides, besides novel test methodologies, a collective insight into the emerging aspects of testing. This, I think, is beneficial to practicing engineers and researchers both of whom must stay at the forefront of technology. [ ] This latest addition to the Frontiers Series is destined to serve an important role."



From the Foreword by Vishwani D. Agrawal, Consulting Editor Frontiers in Electronic Testing Book Series

Foreword xiii
by Vishwani D. Agrawal
Preface xvii
by Dimitris Gizopoulos
Contributing Authors xxiii
Dedication xxv
Chapter 1 Defect-Oriented Testing 1(42)
by Robert C. Aitken
1.1 History of Defect-Oriented Testing
2(2)
1.2 Classic Defect Mechanisms
4(4)
1.2.1 Shorts
4(2)
1.2.2 Opens
6(1)
1.2.3 Parametric Changes
7(1)
1.3 Defect Mechanisms in Advanced Technologies
8(6)
1.3.1 Copper-related Defects
8(2)
1.3.2 Optical Defects
10(2)
1.3.3 Design-related Defects
12(2)
1.4 Defects and Faults
14(14)
1.4.1 Uses of Fault Models
15(1)
1.4.2 Single Stuck-at Faults
16(1)
1.4.3 Bridging Faults
17(5)
1.4.4 Open Fault Models
22(2)
1.4.5 Timing-related or Delay Faults
24(3)
1.4.6 IDDQ Models
27(1)
1.5 Defect-Oriented Test Types
28(6)
1.5.1 Logic Tests
28(1)
1.5.2 Current-based Tests
29(2)
1.5.3 Delay Test
31(1)
1.5.4 Very Low Voltage
32(1)
1.5.5 Stress Testing
33(1)
1.6 Experimental Results
34(5)
1.6.1 Fault Coverage, Scan vs. Functional
34(1)
1.6.2 Effectiveness of IDDQ, Scan, At-speed Tests
34(5)
1.6.3 Statistical Post Processing
39(1)
1.7 Future Trends and Conclusions
39(1)
Acknowledgments
40(1)
References
40(3)
Chapter 2 Failure Mechanisms and Testing in Nanometer Technologies 43(34)
by Jaume Segura, Charles Hawkins and Jerry Soden
2.1 Scaling CMOS Technology
44(33)
2.1.1 Device Scaling
45(6)
2.1.2 Interconnect Scaling
51(1)
2.1.3 Parameter Variations
52(3)
2.1.4 Noise
55(2)
2.2 Failure Modes in Nanometer Technologies
57(8)
2.2.1 Bridge Defects
57(3)
2.2.2 Open Circuit Defects
60(1)
2.2.3 Parametric Failures
61(4)
2.3 Test Methods for Nanometer ICs
65(8)
2.3.1 Impact of Technology Scaling on Testing
66(1)
2.3.2 Dealing with Background Current Increase
67(1)
2.3.3 Noise-tolerant Techniques
68(4)
2.3.4 Impact of Variation on Delay
72(1)
2.4 Conclusion 73
References
73(4)
Chapter 3 Silicon Debug 77(32)
by Doug Josephson and Bob Gottlieb
3.1 Introduction
77(2)
3.2 Silicon Debug History
79(1)
3.3 Silicon Debug Process
80(29)
3.3.1 Post-silicon Validation
80(2)
3.4 Debug Flow
82(1)
3.4.1 Step 1: Control the Failure
82(2)
3.4.2 Step 2: Isolate the Failing Circuit
84(5)
3.4.3 Step 3: Root Cause the Failure
89(2)
3.4.4 Step 4: Try to Expand the Problem
91(1)
3.5 Circuit Failures
92(9)
3.5.1 Speedpaths
92(1)
3.5.2 Mintime Races
92(2)
3.5.3 Charge Sharing
94(2)
3.5.4 Interconnect Noise
96(2)
3.5.5 Leakage
98(2)
3.5.6 Manufacturability
100(1)
3.6 A Case Study in Silicon Debug
101(4)
3.7 Future Challenges for Silicon Debug
105(1)
3.8 Conclusion
106(1)
Acknowledgements
107(1)
References
107(2)
Chapter 4 Delay Testing 109(32)
by Adam Cron
4.1 Introduction
109(1)
4.1.1 Why Delay Testing
109(1)
4.1.2 Why Now
110(1)
4.2 Delay Test Basics
110(6)
4.2.1 Transition Delay Basics
114(1)
4.2.2 Path Delay Basics
115(1)
4.3 Test Application
116(5)
4.3.1 Scan Architectures
116(1)
4.3.2 Last-Shift-Launch
116(2)
4.3.3 System-Clock-Launch
118(1)
4.3.4 Hybrid Launch
119(1)
4.3.5 BIST and Delay Testing
119(1)
4.3.6 Philosophy and Delay Test Application
120(1)
4.4 Delay Test Details
121(4)
4.4.1 Clock Domain Issues
121(3)
4.4.2 I/O Issues
124(1)
4.5 Vector Generation
125(4)
4.5.1 Last-Shift-Launch
126(1)
4.5.2 System-Clock-Launch
126(1)
4.5.3 Fault Model Tweaks
127(1)
4.5.4 Selecting Faults
127(2)
4.6 Chip Design Constructs
129(3)
4.6.1 Phase-Locked Loops (PLLs)
129(1)
4.6.2 Core Test Support
130(2)
4.6.3 I/O Loopback
132(1)
4.7 ATE Requirements
132(4)
4.7.1 I/0 Requirements
133(1)
4.7.2 Speed Requirements
133(2)
4.7.3 Power Requirements
135(1)
4.8 Conclusions: Tests vs. Defects
136(1)
Acknowledgements
137(1)
References
137(4)
Chapter 5 High-Speed Digital Test Interfaces 141(38)
by Wolfgang Maichen
5.1 New Concepts
141(10)
5.1.1 Introduction
141(2)
5.1.2 Transmission Lines
143(8)
5.2 Technology and Design Techniques
151(16)
5.2.1 Parasitics Minimization
151(3)
5.2.2 Loss Mitigation
154(3)
5.2.3 Differential Signaling
157(3)
5.2.4 Termination
160(3)
5.2.5 Power Supply and Decoupling
163(4)
5.3 Characterization and Modeling
167(9)
5.3.1 Characterization Techniques
168(4)
5.3.2 Path Modeling
172(3)
5.3.3 Power Distribution System Modeling
175(1)
5.4 Outlook
176(1)
References
177(2)
Chapter 6 DFT-Oriented, Low-Cost Testers 179(38)
by Al Crouch and Geir Eide
6.1 Introduction
180(4)
6.1.1 Historical Perspective on Structural Test
182(2)
6.2 Test Cost – the Chicken and the Low Cost Tester
184(4)
6.2.1 Schedule, Work Product, and Time-to-Market
184(2)
6.2.2 Manufacturing Test Cost
186(2)
6.3 Tester Use Models
188(2)
6.4 Why and When is DFT Low Cost?
190(14)
6.4.1 Functional vs. Structural Test
190(1)
6.4.2 Structural Test, DFT, and Cost
191(3)
6.4.3 Test Development Automation
194(2)
6.4.4 Defect Coverage and Fault Models
196(3)
6.4.5 DFT and First Silicon Validation
199(2)
6.4.6 DFT and Device Characterization
201(2)
6.4.7 DFT and Yield Learning
203(1)
6.5 What does Low Cost have to do with the Tester?
204(9)
6.5.1 What Makes a Tester Expensive?
204(3)
6.5.2 Achieving Test Goals Without Precision, Accuracy, Flexibility
207(2)
6.5.3 The Next Step in Test Cost Reduction – the Test Interface
209(3)
6.5.4 The LCST is Not the Silver Bullet
212(1)
6.6 Life, the Universe, and Everything
213(2)
References
215(1)
Recommended Reading
216(1)
Chapter 7 Embedded Cores and System-on-Chip Testing 217(46)
by Rubin Parekhji
7.1 Embedded Cores and SOCs
218(1)
7.2 Design and Test Paradigm with Cores and SOCs
219(3)
7.2.1 Classification and Use of Embedded Cores
219(1)
7.2.2 Components of an SOC
220(2)
7.3 DFT for Embedded Cores and SOCs
222(6)
7.3.1 Conventional DFT Techniques
222(1)
7.3.2 DFT for Embedded Cores
223(3)
7.3.3 DFT for SOCs
226(2)
7.4 Test Access Mechanisms
228(4)
7.4.1 Test Interface Control Requirements
228(1)
7.4.2 1149.1 JTAG TAP Interface
229(1)
7.4.3 IEEE 1500 Standard Test Interface
230(2)
7.5 ATPG for Embedded Cores and SOCs
232(4)
7.5.1 Limitations of Conventional ATPG
232(1)
7.5.2 Use of Scan Models
233(2)
7.5.3 SOC Test Coverage Estimation
235(1)
7.6 SOC Test Modes
236(5)
7.6.1 Role of Test Modes
236(1)
7.6.2 Design and Categories of Test Modes
237(2)
7.6.3 Test Pin Requirements
239(1)
7.6.4 Test Mode Selection Mechanisms
239(1)
7.6.5 Examples of Complex Test Modes
240(1)
7.7 Design for At-speed Testing
241(7)
7.7.1 Need for At-speed Testing
241(1)
7.7.2 Requirements for SOC At-speed Test
242(1)
7.7.3 Functional Tests for At-speed Testing
243(1)
7.7.4 Scan Design and Scan Control
244(1)
7.7.5 Clock Control for At-speed Testing
244(2)
7.7.6 Handling Violating Paths
246(1)
7.7.7 Test Control Through I/Os
247(1)
7.7.8 Pattern Generation Techniques
247(1)
7.8 Design for Memory and Logic BIST
248(9)
7.8.1 BIST Overview
248(1)
7.8.2 Design Techniques for Memory BIST
249(3)
7.8.3 Design Techniques for Logic BIST
252(3)
7.8.4 Functional BIST
255(2)
7.8.5 SOC BIST Architecture
257(1)
7.9 Conclusion
257(2)
Acknowledgements
259(1)
References
259(4)
Chapter 8 Embedded Memory Testing 263(38)
by R. Dean Adams
8.1 Introduction
263(4)
8.2 The Memory Design Under Test
267(34)
8.2.1 Static Memory
268(3)
8.2.2 Register Files
271(1)
8.2.3 Dual Port Memories
272(2)
8.2.4 Content Addressable Memories
274(1)
8.2.5 Dynamic Random Access Memories
274(2)
8.3 Memory Faults
276(6)
8.4 Memory Test Patterns
282(1)
8.4.1 Pattern Nomenclature
283(1)
8.4.2 Key March Patterns
284(3)
8.4.3 Memory Data Backgrounds
287(2)
8.4.4 CAM Test Patterns
289(1)
8.5 Self Test
290(5)
8.6 Advanced Memories & Technologies
295(3)
8.7 Conclusions
298(1)
References
298(3)
Chapter 9 Mixed-Signal Testing and DfT 301(36)
by Stephen Sunter
9.1 A Brief History
302(8)
9.1.1 Functional vs. Structural Test
303(1)
9.1.2 Testing
304(1)
9.1.3 Design-for-Test
305(2)
9.1.4 Fault Modeling
307(3)
9.2 The State of the Art
310(11)
9.2.1 Testing
311(7)
9.2.2 DfT
318(2)
9.2.3 Fault Modeling
320(1)
9.3 Advances in the Last 10 Years
321(8)
9.3.1 Testing
322(1)
9.3.2 DfT
323(6)
9.3.3 Fault Modeling
329(1)
9.4 Emerging Techniques and Directions
329(2)
9.4.1 Testing
330(1)
9.4.2 DfT
330(1)
9.5 EDA Tools for Mixed-Signal Testing
331(1)
9.5.1 Testing
331(1)
9.5.2 DfT
332(1)
9.5.3 Fault Modeling
332(1)
9.6 Future Directions
332(2)
References
334(3)
Chapter 10 RF Testing 337(34)
by Randy Wolf, Mustapha Slamani, John Ferrario and Jayendra Bhagat
10.1 Introduction
337(2)
10.2 Testing RF ICs
339(2)
10.2.1 RF IC Categories
339(1)
10.2.2 RF Test Challenges
340(1)
10.3 RF Test Cost Reduction Factors
341(5)
10.3.1 Resources and Test Time Cost
342(2)
10.3.2 Handler
344(2)
10.4 Test Hardware
346(10)
10.4.1 Universal Test Board
347(1)
10.4.2 RF Test Function Sub-Circuit Design
348(5)
10.4.3 Complete Test Architecture
353(3)
10.5 Hardware Development Process
356(3)
10.6 High Frequency Simulation Tools
359(8)
10.6.1 Schematic Simulation
359(3)
10.6.2 2.5D RF Board Simulation
362(3)
10.6.3 3D RF Socket and Package Modeling
365(2)
10.7 Device Under Test Interface
367(1)
10.7.1 Sockets
367(1)
10.7.2 Wafer Probes
367(1)
10.8 Conclusions
368(1)
Acknowledgements
368(1)
References
368(3)
Chapter 11 Loaded Board Testing 371(36)
by Kenneth P. Parker
11.1 The Defect Space at Board Test
372(6)
11.1.1 What is a "Defect"?
372(1)
11.1.2 What is a "Fault"?
373(1)
11.1.3 The "PCOLA/SOQ" Model
374(2)
11.1.4 Test Coverage
376(2)
11.2 In-Circuit Test (ICT)
378(21)
11.2.1 Unpowered Shorts Tests
380(4)
11.2.2 Unpowered Analog Tests
384(7)
11.2.3 Powered In-Circuit Digital Tests
391(3)
11.2.4 Boundary-Scan Tests
394(3)
11.2.5 Powered Mixed-Signal Tests
397(1)
11.2.6 Pros and Cons of ICT
398(1)
11.3 Loaded Board Inspection Systems
399(6)
11.3.1 Automatic Optical Inspection (A0I)
400(2)
11.3.2 Automatic X-Ray Inspection (AXI)
402(2)
11.3.3 Pros and Cons of Inspection
404(1)
11.4 The Future of Board Test
405(1)
References
406(1)
Index 407


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