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E-raamat: Analog-to-Digital Conversion

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  • Ilmumisaeg: 15-Mar-2022
  • Kirjastus: Springer Nature Switzerland AG
  • Keel: eng
  • ISBN-13: 9783030908089
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Analog-to-Digital ConversionSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 15-Mar-2022
  • Kirjastus: Springer Nature Switzerland AG
  • Keel: eng
  • ISBN-13: 9783030908089
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This textbook is appropriate for use in graduate-level curricula in analog-to-digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters.  It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, Nyquist architectures and sigma-delta modulation.  This book presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level.

This new, fourth edition emphasizes novel calibration concepts, the specific requirements of systems, the consequences of advanced technology and the need for a more statistical approach to accuracy. Pedagogical enhancements to this edition include additional, new exercises, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner's perspective, wherever appropriate. Considerable background information and practical tips, from designing a PCB, to lay-out aspects, to trade-offs on system level, complement the discussion of basic principles, making this book a valuable reference for the experienced engineer.

1 Introduction
1(6)
References
6(1)
2 Mathematics
7(42)
2.1 Algebra and Trigonometry
8(24)
2.1.1 Derivatives and Integrals
12(1)
2.1.2 Taylor series
13(2)
2.1.3 Fourier Transform
15(2)
2.1.4 Fourier Series
17(4)
2.1.5 Linearity and Distortion
21(4)
2.1.6 Laplace Transform
25(5)
2.1.7 z-Transform
30(2)
2.2 Statistics
32(17)
2.2.1 Basic Statistical Operations
34(2)
2.2.2 Poisson and Gauss Distributions
36(6)
2.2.3 Practical Estimation
42(2)
2.2.4 Correlation
44(2)
2.2.5 Functions of Statistical Variables
46(2)
References
48(1)
3 Electrical Theory
49(62)
3.1 Resistivity
50(14)
3.1.1 Power and Temperature
53(2)
3.1.2 Voltage and Temperature Coefficient
55(1)
3.1.3 Measuring Resistance
55(1)
3.1.4 Electromigration
56(1)
3.1.5 Thermal Noise
57(4)
3.1.6 1/f Noise
61(3)
3.1.7 Shot Noise
64(1)
3.2 Maxwell Equations
64(16)
3.2.1 Inductors
70(2)
3.2.2 Energy in a Coil
72(1)
3.2.3 Straight-Wire Inductance
72(2)
3.2.4 Skin Effect and Eddy Current
74(1)
3.2.5 Transformer
74(2)
3.2.6 Capacitors
76(2)
3.2.7 Energy in a Capacitor
78(1)
3.2.8 Coaxial Cable
78(2)
3.3 Network Theory
80(31)
3.3.1 Kirchhoff's Laws, Thevenin, Norton, and Superposition
81(2)
3.3.2 Energy and Power
83(3)
3.3.3 Digital Power Consumption and Partial Charging
86(2)
3.3.4 Two-Port Networks
88(1)
3.3.5 Feedback
89(3)
3.3.6 Bode Plot
92(2)
3.3.7 Time Constant and Bandwidth
94(2)
3.3.8 Filters
96(5)
3.3.9 RLC Filters
101(4)
3.3.10 Sallen-Key and gm -- C Filters
105(3)
3.3.11 Gyrator
108(2)
References
110(1)
4 Semiconductors
111(68)
4.1 Semiconductor Materials
111(8)
4.1.1 Bandgap and Boltzmann
111(4)
4.1.2 Semiconductor Resistivity
115(2)
4.1.3 Mott--Gurney Law
117(1)
4.1.4 Temperature and Voltage Coefficients
118(1)
4.1.5 Matching of Resistors
119(1)
4.2 PN-Junction
119(13)
4.2.1 Current in a Diode
122(5)
4.2.2 Temperature Behavior
127(1)
4.2.3 Linearization of Diodes
128(2)
4.2.4 Diode-Based Circuits
130(2)
4.3 Bipolar Junction Transistor
132(5)
4.3.1 Concentrations in a Bipolar Transistor
132(2)
4.3.2 Bipolar Circuits
134(3)
4.3.3 Darlington Pair
137(1)
4.4 MOS Capacitor
137(8)
4.4.1 Gate Capacitance
137(4)
4.4.2 Capacitors Between Layers
141(2)
4.4.3 Voltage and Temperature Coefficient
143(1)
4.4.4 Matching of Capacitors
144(1)
4.5 The MOS Transistor
145(34)
4.5.1 Different Operating Regimes
145(3)
4.5.2 MOS Transistor Current
148(5)
4.5.3 Threshold Voltage
153(1)
4.5.4 Weak-Inversion Current
154(2)
4.5.5 Large Signal and Small Signal
156(1)
4.5.6 Drain Voltage Modulation
157(1)
4.5.7 Output Impedance
158(1)
4.5.8 Matching of MOS Transistors
159(2)
4.5.9 High-Frequency Behavior
161(1)
4.5.10 Leakage
162(2)
4.5.11 Temperature Coefficient
164(2)
4.5.12 Noise in MOS Transistors
166(1)
4.5.13 Noise Cancellation
167(1)
4.5.14 Latch-up
167(2)
4.5.15 Enhancement and Depletion Transistors
169(1)
4.5.16 Advanced Device Architectures
170(3)
4.5.17 MOS Models
173(3)
References
176(3)
5 Electronic Circuits
179(68)
5.1 Basic Circuits
179(22)
5.1.1 Classification of Amplifiers
179(3)
5.1.2 One-Transistor Amplifier
182(2)
5.1.3 Inverter and Latch
184(2)
5.1.4 Source Follower
186(2)
5.1.5 Differential Pair
188(2)
5.1.6 Differential Difference Pair
190(1)
5.1.7 Degeneration
191(2)
5.1.8 Mixers and Variable Gain Amplifiers
193(1)
5.1.9 Current Mirror
194(2)
5.1.10 Cascode Variants
196(3)
5.1.11 Gain Boosting
199(2)
5.2 Operational Amplifiers
201(28)
5.2.1 Single-Stage Amplifier
202(1)
5.2.2 Folded Cascode Amplifier
203(3)
5.2.3 Miller Operational Amplifier
206(4)
5.2.4 Choosing the W/L Ratios in a Miller Opamp
210(5)
5.2.5 Dominant Pole Amplifier
215(1)
5.2.6 Feedback in Electronic Circuits
215(3)
5.2.7 Biasing Circuits
218(2)
5.2.8 Opamps and OTAs
220(4)
5.2.9 Switched-Capacitor Circuits
224(3)
5.2.10 Differential Design
227(2)
5.3 Oscillators
229(18)
5.3.1 LC Oscillators
229(2)
5.3.2 Quartz Oscillators
231(2)
5.3.3 RC Oscillators
233(2)
5.3.4 Phase-Locked Loop
235(1)
5.3.5 Oscillators: Phase Noise
236(3)
5.3.6 Jitter
239(5)
References
244(3)
6 Accuracy: Deterministic and Random Errors
247(70)
6.1 Design by Ratio
247(1)
6.2 Variability
248(2)
6.3 Deterministic Electrical Offsets
250(12)
6.3.1 Equal Dimensions
250(1)
6.3.2 Offset Caused by Electrical Differences
251(2)
6.3.3 Capacitors
253(4)
6.3.4 Resistors
257(2)
6.3.5 Linear Gradient
259(1)
6.3.6 Temperature Gradients
260(2)
6.4 Technology and Accuracy
262(19)
6.4.1 Lithography
262(3)
6.4.2 Proximity Effects
265(4)
6.4.3 Implantation Effects
269(2)
6.4.4 Offset Caused by Stress
271(4)
6.4.5 Issues with Wiring
275(1)
6.4.6 Offset Mitigation
276(5)
6.5 Random Matching
281(21)
6.5.1 Random Fluctuations in Devices
281(2)
6.5.2 Poisson and Gauss
283(1)
6.5.3 MOS Threshold Mismatch
284(5)
6.5.4 Current Factor Mismatch
289(1)
6.5.5 Current Mismatch in Strong and Weak Inversion
290(3)
6.5.6 Mismatch for Various Processes
293(5)
6.5.7 Application to Other Components
298(2)
6.5.8 Advanced Device Architectures
300(1)
6.5.9 Modeling Remarks
300(2)
6.6 Design Consequences
302(15)
6.6.1 Analog Design
303(4)
6.6.2 Digital Design
307(3)
6.6.3 Drift
310(1)
6.6.4 Limits of Power and Accuracy
310(3)
References
313(4)
7 Sampling
317(64)
7.1 Sampling in Time and Frequency
317(10)
7.1.1 Dirac Sequence
317(2)
7.1.2 Sampling Signals
319(5)
7.1.3 Sampling Limit: Nyquist Criterion
324(3)
7.2 Sampling Aspects
327(12)
7.2.1 Down-Sampling
327(2)
7.2.2 Subsampling and Decimation
329(2)
7.2.3 Alias Filter
331(4)
7.2.4 Alias Removal After Digital-to-Analog Conversion
335(1)
7.2.5 Getting Around Nyquist?
336(2)
7.2.6 Fourier Uncertainty
338(1)
7.3 Modulation and Chopping
339(6)
7.3.1 Modulation
339(3)
7.3.2 Chopping
342(3)
7.4 Reconstruction of Sampled Data
345(4)
7.5 Noise
349(9)
7.5.1 Sampled Noise
350(5)
7.5.2 Differential Noise
355(3)
7.6 Jitter
358(9)
7.6.1 Jitter of the Sampling Pulse
358(6)
7.6.2 Driving a Sampling Pulse
364(3)
7.6.3 Optical Sampling
367(1)
7.7 Time-Discrete Filtering
367(14)
7.7.1 Finite Impulse Response Filters
367(6)
7.7.2 Half-Band Filters
373(2)
7.7.3 IIR Filters
375(4)
References
379(2)
8 Sample-and-Hold Circuits
381(44)
8.1 Track-and-Hold and Sample-and-Hold Circuits
381(2)
8.2 Artifacts in T&H Circuits
383(6)
8.2.1 Pedestal Step
383(3)
8.2.2 Droop
386(1)
8.2.3 Hold-Mode Feed-Through
387(2)
8.3 Capacitor and Switch Implementations
389(12)
8.3.1 Capacitor
389(1)
8.3.2 Switch Impedance
389(3)
8.3.3 Complementary Switch
392(1)
8.3.4 High Voltages
393(1)
8.3.5 Bootstrap Techniques
394(5)
8.3.6 Threshold Modulation
399(1)
8.3.7 Bottom-Plate Sampling
399(2)
8.4 T&H Circuit Topologies
401(24)
8.4.1 Driving a T&H Configuration
401(1)
8.4.2 Buffering the Hold Capacitor
402(3)
8.4.3 Switched-Capacitor T&H Circuits
405(2)
8.4.4 Flip-Around T&H Circuit
407(1)
8.4.5 Offset and Noise in Flip-Around Circuits
408(2)
8.4.6 Differential Flip-Around Architecture
410(2)
8.4.7 MDAC: Amplifying T&H Circuit
412(2)
8.4.8 T&H with a Level-Shifting Opamp
414(1)
8.4.9 Correlated Double Sampling
414(2)
8.4.10 Bipolar T&H Circuit
416(3)
8.4.11 Distortion and Noise
419(3)
References
422(3)
9 Quantization
425(46)
9.1 Resolution
425(3)
9.2 Quantization Error
428(7)
9.2.1 1-Bit Quantization
428(2)
9.2.2 2-6 Bit Quantization
430(1)
9.2.3 7-Bit and Higher Quantization
431(4)
9.3 Signal-to-Quantization Error Ratio
435(7)
9.3.1 SNQR Definition
435(3)
9.3.2 Related Definitions
438(2)
9.3.3 Nyquist Rate and Oversampled Architectures
440(2)
9.4 Linearity
442(5)
9.4.1 Integral Non-Linearity (INL)
442(2)
9.4.2 Differential Non-Linearity (DNL)
444(3)
9.5 Modeling INL and DNL
447(11)
9.5.1 From INL to Distortion
447(3)
9.5.2 DNL and Quantization
450(3)
9.5.3 Non-uniform Quantization
453(1)
9.5.4 Dither
454(4)
9.6 Figure-of-Merit
458(13)
9.6.1 Figure-of-Merit: Schreier
458(1)
9.6.2 Figure-of-Merit: Walden
459(4)
9.6.3 Figure-of-Merit: Digital-to-Analog Converters
463(1)
9.6.4 Figure-of-Merit: Risks
464(5)
References
469(2)
10 Reference Circuits
471(40)
10.1 General Requirements
471(3)
10.2 Bandgap Voltage Reference Circuits
474(17)
10.2.1 Principle
474(6)
10.2.2 Bipolar Devices in CMOS
480(2)
10.2.3 Standard CMOS Bandgap Circuit
482(4)
10.2.4 Artifacts: Start-Up
486(1)
10.2.5 Artifacts: Bandwidth
487(2)
10.2.6 Artifacts: Mismatch and Noise
489(2)
10.3 Bandgap Reference Circuits
491(10)
10.3.1 Bandgap Circuits in Bipolar Technology
491(2)
10.3.2 Current-Mode Bandgap Circuit
493(2)
10.3.3 Low-Voltage Bandgap Circuits
495(3)
10.3.4 Second Order Compensation
498(3)
10.4 Alternative References
501(10)
10.4.1 Weak Inversion
501(2)
10.4.2 DTMOST Reference Circuit
503(2)
10.4.3 Other Technological Options
505(4)
References
509(2)
11 Digital-to-Analog Conversion
511(88)
11.1 Representations
511(14)
11.1.1 Digital Codes
511(2)
11.1.2 Unary Representation
513(2)
11.1.3 Unary: INL and DNL
515(3)
11.1.4 Binary Representation
518(1)
11.1.5 Binary: INL and DNL
519(3)
11.1.6 Segmentation
522(1)
11.1.7 Segmented: INL and DNL
523(2)
11.2 Voltage-Domain Digital-to-Analog Conversion
525(20)
11.2.1 Resistor Ladders
525(2)
11.2.2 Resistor Ladder: Dynamic Behavior
527(2)
11.2.3 Practical Issues in Resistor Ladders
529(2)
11.2.4 Accuracy in Resistors Ladders
531(5)
11.2.5 R-2R Ladders
536(1)
11.2.6 Accuracy in R-2R Ladders
537(2)
11.2.7 A Video Resistor Ladder Digital-to-Analog Converter
539(6)
11.3 Current-Domain Digital-to-Analog Conversion
545(28)
11.3.1 Buffered Current-Domain Digital-to-Analog Converters
545(2)
11.3.2 Current-Steering Digital-to-Analog Conversion
547(2)
11.3.3 Matrix Decoding
549(3)
11.3.4 INL and DNL
552(4)
11.3.5 Current Cell
556(3)
11.3.6 Switching the Current Cells
559(2)
11.3.7 Calibration of Current Sources
561(3)
11.3.8 Sorting and Selecting
564(4)
11.3.9 Performance Limits
568(3)
11.3.10 Semi-Digital Filters
571(2)
11.4 Charge-Domain Digital-to-Analog Conversion
573(8)
11.4.1 Switched-Capacitor Digital-to-Analog Conversion
573(1)
11.4.2 Charge-Redistribution Converters
574(3)
11.4.3 RF Digital-to-Analog Converters
577(2)
11.4.4 Bridge Capacitor
579(2)
11.5 Algorithmic Digital-to-Analog Conversion
581(6)
11.5.1 Conversion by Passive Redistribution
581(2)
11.5.2 Diophantine Digital-to-Analog Conversion
583(4)
11.6 Time-Domain Digital-to-Analog Conversion
587(12)
11.6.1 1-Bit Digital-to-Analog Converter
587(1)
11.6.2 Time-Domain Signals
588(1)
11.6.3 Jitter in the Time Domain
589(2)
11.6.4 Class-D Amplifiers
591(4)
References
595(4)
12 Comparators
599(44)
12.1 Comparator Classification
599(14)
12.1.1 Limiting Amplifier
600(2)
12.1.2 Hysteresis Comparator
602(2)
12.1.3 Resistive Pre-amplification
604(3)
12.1.4 Integrating Pre-amplification
607(3)
12.1.5 Floating Inverter
610(1)
12.1.6 Regenerative Comparator
610(1)
12.1.7 Latch
611(2)
12.2 Comparator Issues
613(10)
12.2.1 Metastability and Bit Error Rate
613(4)
12.2.2 Accuracy
617(2)
12.2.3 Kick-Back
619(1)
12.2.4 Hysteresis
620(3)
12.3 Comparator Examples
623(20)
12.3.1 Comparators: Amplifier Based
623(5)
12.3.2 StrongARM Comparators
628(4)
12.3.3 Double-Tail Comparator
632(3)
12.3.4 Calibrated Comparators
635(2)
12.3.5 T&H Plus Comparator
637(2)
References
639(4)
13 Flash Analog-to-Digital Conversion
643(38)
13.1 Classification of Analog-to-Digital Converters
643(2)
13.2 Traditional Flash Converters
645(17)
13.2.1 Ladder Implementation
649(1)
13.2.2 Comparator Random Mismatch
650(3)
13.2.3 Comparator Yield Loss
653(5)
13.2.4 Decoder
658(4)
13.3 Advanced Schemes
662(14)
13.3.1 Averaging
662(2)
13.3.2 Interpolation
664(2)
13.3.3 Frequency Dependent Mismatch
666(1)
13.3.4 Time Interpolation
667(2)
13.3.5 Folding Converter
669(3)
13.3.6 Mismatch Dominated Converter
672(1)
13.3.7 Technology Scaling for Flash Converters
672(2)
13.3.8 Digital Output Power
674(2)
13.4 Power, Bandwidth, and Resolution
676(5)
References
677(4)
14 Subranging and Two-Step Analog-to-Digital Conversion
681(18)
14.1 Subranging Architecture
681(8)
14.1.1 Overrange
683(1)
14.1.2 Monkey-Switching
684(5)
14.2 Two-Step Architecture
689(10)
14.2.1 Overrange in Two-Step Architectures
692(4)
References
696(3)
15 Pipeline Analog-to-Digital Conversion
699(48)
15.1 1-Bit Pipeline Converters
699(15)
15.1.1 Multiplying Digital-to-Analog Converter (MDAC)
699(3)
15.1.2 MDAC Implementation
702(2)
15.1.3 Error Sources in Pipeline Converters
704(1)
15.1.4 Multiply-by-Two Errors
705(3)
15.1.5 Bandwidth and Settling
708(2)
15.1.6 Noise
710(2)
15.1.7 Reduced Radix Converters with Calibration
712(2)
15.2 1.5-Bit Pipeline Analog-to-Digital Converter
714(13)
15.2.1 Redundancy
717(1)
15.2.2 Design of an MDAC Stage
718(4)
15.2.3 Multi-Bit MDAC Stage
722(5)
15.3 Pipeline Variations
727(10)
15.3.1 Opamp Sharing
727(2)
15.3.2 Sample-and-Hold-Less Conversion
729(1)
15.3.3 Decoupled Capacitors
730(1)
15.3.4 Continuous-Time Front-End
730(1)
15.3.5 Other Forms of MDAC Amplification
731(6)
15.4 Algorithmic Converters
737(4)
15.5 Power, Bandwidth, and Resolution
741(6)
References
744(3)
16 Successive Approximation Conversion
747(48)
16.1 The Algorithm
747(3)
16.2 Charge-Redistribution Conversion
750(13)
16.2.1 Basic Operation
750(3)
16.2.2 Parasitic Capacitor
753(1)
16.2.3 Top-Plate or Bottom-Plate Input
753(2)
16.2.4 Bridge Capacitor
755(4)
16.2.5 Digital Controller
759(4)
16.3 Artifacts and Mitigations
763(15)
16.3.1 Speed, Noise, and Kick-Back
763(2)
16.3.2 Accuracy and Calibration
765(3)
16.3.3 Redundancy for Comparator Errors
768(3)
16.3.4 Sub-Radix-2 Base
771(2)
16.3.5 Energy
773(5)
16.4 Alternative Successive Approximation Converters
778(17)
16.4.1 Two-Step Architectures with SAR
778(3)
16.4.2 Passive Charge Division
781(1)
16.4.3 Multi-Bit Comparison
781(1)
16.4.4 Noise-Shaping SAR
782(1)
16.4.5 Mismatch-Error Shaping
783(1)
16.4.6 Resistive Successive Approximation Converter
784(4)
16.4.7 Power, Bandwidth, and Resolution
788(4)
References
792(3)
17 Linear and Time-Based Conversion
795(18)
17.1 Linear Approximation Converters
795(3)
17.1.1 Counting Converter
795(2)
17.1.2 Tracking Converter
797(1)
17.2 Time-Related Conversion
798(4)
17.2.1 Wilkinson Converter
798(1)
17.2.2 Dual-Slope Converter
798(2)
17.2.3 Pulse-Width Modulation Converter
800(2)
17.3 Voltage-to-Time Conversion
802(6)
17.3.1 Voltage-to-Frequency Conversion
802(3)
17.3.2 Time-to-Digital Conversion
805(2)
17.3.3 Vernier/Nonius Principle
807(1)
17.4 Other Conversion Proposals
808(5)
17.4.1 Level-Crossing Analog-to-Digital Conversion
808(1)
17.4.2 Asynchronous Successive Approximation Conversion
809(1)
17.4.3 Floating-Point Converter
810(1)
References
811(2)
18 Time-Interleaving
813(48)
18.1 The Need for Time Interleaving
813(8)
18.1.1 Time-Domain Interleaving
815(2)
18.1.2 Frequency-Domain View
817(4)
18.2 Input Sampling
821(9)
18.2.1 1 × Buffer
821(2)
18.2.2 Input Driver
823(2)
18.2.3 Signal Distribution
825(3)
18.2.4 Track-and-Hold Implementations
828(2)
18.3 Time-Interleaving Errors
830(13)
18.3.1 Random DC-Offsets Between Channels
831(3)
18.3.2 Random Gain Differences Between Channels
834(1)
18.3.3 Input Sampling Errors
835(5)
18.3.4 Bandwidth Differences
840(2)
18.3.5 Reconstruction Errors
842(1)
18.4 Time-Interleaving Architectures
843(13)
18.4.1 2 × Interleaving
844(2)
18.4.2 3, 4 × Interleaving
846(3)
18.4.3 8 × Interleaving
849(2)
18.4.4 Two-Stage Interleaving
851(5)
18.5 Frequency Multiplexing
856(1)
18.6 Power, Bandwidth, and Resolution
856(5)
References
858(3)
19 Time-Discrete ΣΔ Modulation
861(48)
19.1 Oversampling
862(4)
19.1.1 Oversampling in Analog-to-Digital Conversion
862(2)
19.1.2 Oversampling in Digital-to-Analog Conversion
864(2)
19.2 Noise Shaping
866(9)
19.2.1 Higher Order Noise Shaping
870(5)
19.3 ΣΔ Modulation
875(8)
19.3.1 A Quantizer in a Feedback Loop
875(4)
19.3.2 Linearization
879(4)
19.4 Time-Discrete ΣΔ Modulation
883(16)
19.4.1 First Order Modulator
884(1)
19.4.2 Second Order Modulator
885(3)
19.4.3 Cascade of Integrators
888(4)
19.4.4 Input Feed-Forward Modulator
892(1)
19.4.5 Circuit Design Considerations
893(1)
19.4.6 Overload
894(1)
19.4.7 Decimation
895(4)
19.5 Higher Order Time-Discrete Converters
899(4)
19.5.1 Cascaded ΣΔ Modulator
899(3)
19.5.2 0-LMASH
902(1)
19.6 ΣΔ Digital-to-Analog Conversion
903(6)
19.6.1 Single-Loop Conversion
903(2)
19.6.2 Cascaded Digital-to-Analog Conversion
905(2)
References
907(2)
20 Time-Continuous ΣΔ Modulation
909(42)
20.1 First and Second Order Modulator
909(17)
20.1.1 Linearized Model
909(5)
20.1.2 Higher Order E A Converters
914(6)
20.1.3 Digital-to-Analog Converter in the Loop
920(2)
20.1.4 Excess Loop Delay in Time-Continuous E A Conversion
922(1)
20.1.5 Meta-Stability
923(1)
20.1.6 Latency
924(1)
20.1.7 Filter Implementations
924(2)
20.2 Time-Discrete and Time-Continuous ΣΔ Conversion
926(3)
20.3 Multi-Bit ΣΔ Conversion
929(3)
20.4 Various Forms of ΣΔ Modulation
932(10)
20.4.1 First Order ΣΔ Modulator with Chopping and Dither
932(2)
20.4.2 Complex ΣΔ Modulation
934(2)
20.4.3 Asynchronous ΣΔ Modulation
936(1)
20.4.4 Bandpass ΣΔ Converter
937(2)
20.4.5 ΣΔ Loop with Noise-Shaping
939(1)
20.4.6 Incremental ΣΔ Converter
940(2)
20.5 Power, Bandwidth, and Resolution
942(9)
References
947(4)
21 Mitigation of Errors
951(20)
21.1 Strategies
951(2)
21.2 Removing the Error
953(5)
21.2.1 Auto-Zero Mechanism
953(1)
21.2.2 Calibration
954(3)
21.2.3 Split Converters
957(1)
21.3 Moving the Error
958(13)
21.3.1 Dithering
958(1)
21.3.2 Chopping
959(1)
21.3.3 Dynamic Element Matching (D.E.M.)
960(4)
21.3.4 Data-Weighted Averaging (D.W.A.)
964(5)
References
969(2)
22 Characterization and Measurement
971(28)
22.1 Test Hardware
972(6)
22.2 Measurement Methods
978(10)
22.2.1 INL and DNL
978(5)
22.2.2 Harmonic Behavior and Coherent Testing
983(3)
22.2.3 Windowing
986(2)
22.3 Special Measurements
988(6)
22.3.1 Noise
988(1)
22.3.2 Bit Error Rate
988(1)
22.3.3 Multi-Tone Power Ratio
989(1)
22.3.4 Differential Gain and Differential Phase
990(3)
22.3.5 Self-Testing
993(1)
22.4 How to Solve a Problem?
994(5)
References
997(2)
Index 999
Marcel Pelgrom received his B.EE, M.Sc, and PhD from the University of Twente, Enschede, The Netherlands. In 1979, he joined the Philips Research Laboratories, where his research has covered topics such as charge coupled devices, MOS matching properties, analog-to-digital conversion, digital image correlation, and various analog building block techniques. He has headed several project teams and was a team leader for highspeed analog-to-digital conversion. From 1996 until 2003, he was a department head for mixed-signal electronics. In addition to various activities concerning industry-academic relations, he was a Philips Research Fellow, which research topics on the edge of design and technology. In 2003, he spent a sabbatical in Stanford University where he served as a consulting professor and in 2014 as a lecturer. From 2006 until 2013, he has been a member of the technical staff at NXP Semiconductors. Dr. Pelgrom was twice an IEEE Distinguished Lecturer and has written over40 publications and seven book chapters, and he holds 37 US patents. He currently lectures at Delft University of Technology, the University of Twente and for MEAD Inc, next to consulting in various companies. He is the 2017 recipient of the IEEE field award Gustav R. Kirchhoff. 
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