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E-raamat: Analog IC Design with Low-Dropout Regulators, Second Edition

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  • Formaat: 528 pages
  • Ilmumisaeg: 27-Mar-2014
  • Kirjastus: McGraw-Hill Professional
  • Keel: eng
  • ISBN-13: 9780071826662
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Analog IC Design with Low-Dropout Regulators, Second EditionSuurem pilt
  • Formaat: 528 pages
  • Ilmumisaeg: 27-Mar-2014
  • Kirjastus: McGraw-Hill Professional
  • Keel: eng
  • ISBN-13: 9780071826662
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Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality, authenticity, or access to any online entitlements included with the product.THE LATEST ANALOG IC DESIGN TECHNIQUESFully revised and expanded to meet the emerging demands of mixedsignal systems, Analog IC Design with Low-Dropout Regulators, Second Edition, teaches analog IC concepts and explains how to use them to design, analyze,and build linear low-dropout (LDO) regulator ICs with bipolar, CMOS, and biCMOS semiconductor process technologies. The book draws physical insight from topics presented and illustrates how to develop and evaluate analog ICs for today's expanding wireless and mobile markets. Practical examples and end-of-chapter review questions reinforce important concepts and techniquesdeveloped in this cutting-edge guide.

LEARN HOW TO:





Evaluate power-supply systems Predict and specify how linear regulators perform and respond to variations in their supplies, loads, and other working conditions Work with semiconductor devices--resistors, capacitors, diodes, and transistors Combine microelectronic components to design current mirrors, differential pairs, differential amplifiers, linear low-dropout regulators, and their variants Close and stabilize feedback control loops that regulate voltages and currents Design circuits that establish reliable bias currents and reference circuits Determine the small-signal dynamics of analog ICs and analog systems Establish independent, stable, noise-free, and predictable power-supply voltages Implement overcurrent, thermal, reverse-battery, and ESD protection Test, measure, and evaluate linear regulator ICs
Preface xv
1 Power-Supply Systems
1(18)
1.1 Regulators in Power Management
1(1)
1.2 Linear versus Switched Regulators
2(5)
1.2.1 Response-Time Tradeoffs
4(1)
1.2.2 Noise
5(1)
1.2.3 Power-Conversion Efficiency
5(2)
1.3 Market Demand
7(3)
1.3.1 System
7(1)
1.3.2 Integration
8(1)
1.3.3 Operational Life
8(1)
1.3.4 Supply Headroom
9(1)
1.4 Power Sources
10(5)
1.4.1 Early Batteries
10(2)
1.4.2 Lithium-Ion Batteries
12(1)
1.4.3 Fuel Cells
13(1)
1.4.4 Nuclear Batteries
14(1)
1.4.5 Energy-Harvesting Transducers
14(1)
1.5 Computer Simulations
15(1)
1.6 Summary
16(1)
1.7 Review Questions
17(2)
2 Linear Regulators
19(32)
2.1 Regions of Operation
19(2)
2.2 Performance Metrics
21(18)
2.2.1 Accuracy
21(12)
2.2.2 Power-Conversion Efficiency
33(3)
2.2.3 Operating Requirements
36(2)
2.2.4 Figures of Merit
38(1)
2.3 Operating Environment
39(5)
2.3.1 The Load
40(2)
2.3.2 Point of Regulation
42(1)
2.3.3 Parasitic Effects
43(1)
2.4 Classification
44(3)
2.4.1 Output Current
44(1)
2.4.2 Dropout
44(1)
2.4.3 Compensation
44(1)
2.4.4 Categories
45(2)
2.5 Block-Level Composition
47(1)
2.6 Summary
48(1)
2.7 Review Questions
49(2)
3 Microelectronic Devices
51(56)
3.1 Resistors
51(6)
3.1.1 Theory of Operation
51(1)
3.1.2 Parasitic Components
52(1)
3.1.3 Layout
53(2)
3.1.4 Absolute and Relative Accuracy
55(2)
3.2 Capacitors
57(4)
3.2.1 Theory of Operation
57(1)
3.2.2 Parasitic Components
58(1)
3.2.3 Layout
59(1)
3.2.4 Absolute and Relative Accuracy
60(1)
3.3 PN-Junction Diodes
61(9)
3.3.1 Theory of Operation
61(4)
3.3.2 Parasitic Components
65(1)
3.3.3 Layout and Matching
66(2)
3.3.4 Small-Signal Model
68(2)
3.4 Bipolar-Junction Transistors
70(10)
3.4.1 Theory of Operation
70(4)
3.4.2 Vertical BJTs
74(1)
3.4.3 Lateral BJTs
75(2)
3.4.4 Substrate BJTs
77(1)
3.4.5 Small-Signal Model
78(2)
3.5 Metal--Oxide--Semiconductor Field-Effect Transistors
80(16)
3.5.1 Theory of Operation
80(7)
3.5.2 Parasitic Capacitances
87(1)
3.5.3 P-Channel MOSFETs
88(1)
3.5.4 Transistor Variations
89(2)
3.5.5 Layout and Matching
91(2)
3.5.6 Small-Signal Model
93(2)
3.5.7 MOS Capacitor
95(1)
3.5.8 Channel Resistor
96(1)
3.6 Junction Field-Effect Transistors
96(6)
3.6.1 Theory of Operation
96(2)
3.6.2 P-Channel JFETs
98(1)
3.6.3 Large-Signal Model
99(1)
3.6.4 Layout and Matching
100(1)
3.6.5 Small-Signal Model
100(2)
3.6.6 Relative Performance
102(1)
3.7 Absolute and Relative Accuracies
102(1)
3.8 Summary
103(2)
3.9 Review Questions
105(2)
4 Single-Transistor Primitives
107(44)
4.1 Two-Port Models
107(2)
4.2 Frequency Response
109(7)
4.2.1 Poles
110(1)
4.2.2 Zeros
111(2)
4.2.3 Miller Split
113(1)
4.2.4 Capacitors-Shunting-Resistors Method
114(2)
4.3 Signal Flow
116(2)
4.3.1 Inputs and Outputs
116(1)
4.3.2 Polarity
116(2)
4.3.3 Single-Transistor Primitives
118(1)
4.4 Common-Emitter/Source Transconductor
118(11)
4.4.1 Large-Signal Operation
118(1)
4.4.2 Small-Signal Model
119(2)
4.4.3 Frequency Response
121(4)
4.4.4 Emitter/Source Degeneration
125(4)
4.5 Common-Base/Gate Current Buffer
129(7)
4.5.1 Large-Signal Operation
130(1)
4.5.2 Small-Signal Model
130(4)
4.5.3 Frequency Response
134(1)
4.5.4 Base Degeneration
135(1)
4.6 Common-Collector/Drain Voltage Follower
136(7)
4.6.1 Large-Signal Operation
136(1)
4.6.2 Small-Signal Model
137(3)
4.6.3 Frequency Response
140(3)
4.7 Small-Signal Generalizations and Approximations
143(5)
4.7.1 Functionality
143(1)
4.7.2 Resistances
144(3)
4.7.3 Frequency Response
147(1)
4.8 Summary
148(2)
4.9 Review Questions
150(1)
5 Analog Building Blocks
151(48)
5.1 Current Mirror
152(8)
5.1.1 Theory of Operation
152(3)
5.1.2 Small-Signal Model
155(1)
5.1.3 Base-Current Correction
156(1)
5.1.4 Voltage-Correcting Cascodes
157(2)
5.1.5 Low-Voltage Cascodes
159(1)
5.2 Differential Pair
160(9)
5.2.1 Large-Signal Operation
162(1)
5.2.2 Differential Signals
163(2)
5.2.3 Common-Mode Signals
165(2)
5.2.4 Emitter/Source Degeneration
167(1)
5.2.5 CMOS Pairs
168(1)
5.3 Base/Gate-Coupled Pair
169(7)
5.3.1 Large-Signal Operation
169(3)
5.3.2 Small-Signal Response
172(2)
5.3.3 Input-Referred Offset and Noise
174(2)
5.4 Differential Stage
176(19)
5.4.1 Large-Signal Operation
177(1)
5.4.2 Differential Signals
178(3)
5.4.3 Common-Mode Signals
181(4)
5.4.4 Input-Referred Offset and Noise
185(3)
5.4.5 Power-Supply Rejection
188(2)
5.4.6 Folding Cascodes
190(5)
5.5 Summary
195(1)
5.6 Review Questions
196(3)
6 Negative Feedback
199(70)
6.1 Feedback Loop
199(3)
6.1.1 Loop Composition
199(1)
6.1.2 Regulation
200(1)
6.1.3 Output Translation
201(1)
6.2 Feedback Effects
202(12)
6.2.1 Sensitivity
202(1)
6.2.2 Impedance
203(3)
6.2.3 Frequency Response
206(3)
6.2.4 Noise
209(2)
6.2.5 Linearity
211(3)
6.3 Configurations
214(7)
6.3.1 Transconductance Amplifier
214(2)
6.3.2 Voltage Amplifier
216(1)
6.3.3 Current Amplifier
217(2)
6.3.4 Transimpedance Amplifier
219(2)
6.4 Analysis
221(30)
6.4.1 Analytical Process
221(3)
6.4.2 Mixers
224(1)
6.4.3 Samplers
225(2)
6.4.4 Transconductance Amplifiers
227(6)
6.4.5 Voltage Amplifiers
233(5)
6.4.6 Current Amplifiers
238(7)
6.4.7 Transimpedance Amplifiers
245(6)
6.5 Stability
251(13)
6.5.1 Response
251(3)
6.5.2 Compensation
254(6)
6.5.3 Out-of-Phase Zero
260(3)
6.5.4 Embedded Loops
263(1)
6.6 Design
264(2)
6.6.1 Design Concepts
264(1)
6.6.2 Architectural Design
264(1)
6.6.3 Frequency Compensation
265(1)
6.7 Summary
266(1)
6.8 Review Questions
267(2)
7 Bias Currents and Reference Circuits
269(36)
7.1 Voltage Primitives
269(2)
7.2 PTAT Current
271(8)
7.2.1 Cross-Coupled Quad
272(1)
7.2.2 Latched Cell
273(6)
7.3 CTAT Current
279(2)
7.3.1 Current-Sampled BJT
279(1)
7.3.2 Voltage-Sampled Diode
280(1)
7.4 Temperature Compensation
281(5)
7.4.1 Error-Compensated BJT Current Reference
283(1)
7.4.2 Diode-Derived Current Reference
284(1)
7.4.3 Error-Compensated Diode-Derived Current Reference
285(1)
7.5 Startup
286(4)
7.5.1 Continuous Startup
286(2)
7.5.2 On-Demand Startup
288(2)
7.6 Frequency Compensation
290(2)
7.7 Suppressing Supply Noise
292(1)
7.8 Bandgap Current Reference
293(3)
7.8.1 BJT-Derived Bandgap Current Reference
293(1)
7.8.2 Diode-Derived Bandgap Current Reference
294(2)
7.9 Bandgap Voltage Reference
296(4)
7.9.1 Current-to-Voltage Translation
296(1)
7.9.2 Output Regulation
296(4)
7.10 Accuracy
300(2)
7.11 Summary
302(1)
7.12 Review Questions
303(2)
8 Small-Signal Response
305(42)
8.1 Equivalent Small-Signal Circuit
306(1)
8.2 Uncompensated Response
307(5)
8.2.1 Relative Capacitances and Resistances
307(2)
8.2.2 Loop Gain
309(3)
8.3 Frequency Compensation
312(8)
8.3.1 Output Compensation
313(4)
8.3.2 Internal Compensation
317(3)
8.4 Power-Supply Rejection
320(21)
8.4.1 Voltage-Divider Model
322(1)
8.4.2 Feed-Through Noise
323(8)
8.4.3 Miller Capacitor
331(2)
8.4.4 Analysis
333(7)
8.4.5 Conclusions
340(1)
8.5 Comparison of Compensation Strategies
341(1)
8.6 Summary
342(2)
8.7 Review Questions
344(3)
9 Integrated Circuits
347(56)
9.1 Design Process
347(1)
9.2 Power Transistors
348(13)
9.2.1 Alternatives
349(3)
9.2.2 Layout
352(9)
9.3 Buffers
361(18)
9.3.1 Driving N-Type Power Transistors
361(3)
9.3.2 Driving P-Type Power Transistors
364(14)
9.3.3 Layout
378(1)
9.4 Error Amplifiers
379(19)
9.4.1 Headroom
379(4)
9.4.2 Power-Supply Rejection
383(2)
9.4.3 Input-Referred Offset
385(4)
9.4.4 Layout
389(9)
9.5 Summary
398(2)
9.6 Review Questions
400(3)
10 Linear Regulators
403(52)
10.1 Low-Dropout Regulators
403(11)
10.1.1 Output-Compensated PMOS
403(5)
10.1.2 Miller-Compensated PMOS
408(6)
10.2 High-Bandwidth Regulators
414(4)
10.2.1 Internally Compensated NMOS
414(4)
10.3 Self-Referenced Regulators
418(11)
10.3.1 Zero-Order Temperature Independence
419(1)
10.3.2 Temperature Compensation
420(9)
10.4 Performance Enhancers
429(16)
10.4.1 Power Transistor
429(4)
10.4.2 Buffer
433(2)
10.4.3 Loop Gain
435(3)
10.4.4 Load Regulation
438(1)
10.4.5 Load-Dump Response
439(3)
10.4.6 Power-Supply Rejection
442(3)
10.5 Current Regulation
445(6)
10.5.1 Current Sources
446(2)
10.5.2 Current Mirrors
448(3)
10.6 Summary
451(1)
10.7 Review Questions
452(3)
11 Protection and Characterization
455(30)
11.1 Protection
455(12)
11.1.1 Overcurrent Protection
456(4)
11.1.2 Thermal Shutdown
460(2)
11.1.3 Reverse-Battery Protection
462(2)
11.1.4 Electrostatic-Discharge Protection
464(3)
11.2 Characterization
467(16)
11.2.1 Emulating the Load
468(1)
11.2.2 Regulation Performance
469(8)
11.2.3 Power Performance
477(2)
11.2.4 Operating Requirements
479(3)
11.2.5 Startup
482(1)
11.3 Summary
483(1)
11.4 Review Questions
483(2)
Index 485
Gabriel Alfonso Rincon-Mora was a Senior Integrated Circuit (IC) Design Team Leader for Texas Instruments from 1994 2003. He was appointed an Adjunct Professor at the Georgia Institute of Technology in 1999, and became a full-time faculty member in 2001. Since 2011, Dr. Rincon-Mora has also been a visiting professor at National Cheng Kung University in Taiwan. He has published 140 papers in scientific publications, written eight books, and has more than 26 commercial power chip designs. Dr. Rincon-Mora is an IEEE Fellow "for contributions to energy and power integrated circuit design" and an Institution of Engineering and Technology (IET) Fellow. His research is on the design and development of silicon-based integrated circuits (ICs) that draw and condition power from tiny batteries, fuel cells, and energy-harnessing generators to supply mobile, portable, and self-sustaining devices like wireless microsensors for biomedical, consumer, industrial, and military applications.
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