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E-raamat: Analysis and Design of Networks-on-Chip Under High Process Variation

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  • Formaat: PDF+DRM
  • Ilmumisaeg: 16-Dec-2015
  • Kirjastus: Springer International Publishing AG
  • Keel: eng
  • ISBN-13: 9783319257662
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Analysis and Design of Networks-on-Chip Under High Process VariationSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 16-Dec-2015
  • Kirjastus: Springer International Publishing AG
  • Keel: eng
  • ISBN-13: 9783319257662
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This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

Introduction.- Network On Chip Aspects.- Interconnection.- Process Variation.- Synchronous And Asynchronous NoC Design Under High Process Variation.- Novel Routing Algorithm.- Simulation Results.- Conclusions.
1 Introduction
1.1 Motivation
2(2)
1.2 Contribution
4(1)
1.3 Book Organization
5(6)
References
5(6)
Part I Background
2 Network on Chip Aspects
11(34)
2.1 Introduction
11(1)
2.2 Synchronization in NoC
11(23)
2.2.1 Synchronous Designs
12(6)
2.2.2 Asynchronous Designs
18(16)
2.3 Routing Algorithms in NoC
34(7)
2.3.1 Classification of Routing Algorithms
34(3)
2.3.2 Routing Issues
37(1)
2.3.3 Routing Algorithm Schemes
38(3)
2.4 Conclusions
41(4)
References
42(3)
3 Interconnection
45(12)
3.1 Introduction
45(1)
3.2 Interconnect Metal Layer
46(1)
3.3 Interconnect Characteristics
46(5)
3.3.1 Interconnect Resistance
47(1)
3.3.2 Interconnect Capacitance
47(3)
3.3.3 Interconnect Inductance
50(1)
3.4 Repeater Design
51(2)
3.5 Repeater Model
53(1)
3.5.1 RC Interconnect
53(1)
3.5.2 RLC Interconnect
54(1)
3.6 Clock Skew
54(1)
3.7 Skew Sources
55(1)
3.8 Conclusions
56(1)
References
56(1)
4 Process Variation
57(14)
4.1 Introduction
57(1)
4.2 Classification of Variation Parameters
57(2)
4.2.1 Systematic Versus Non-systematic Variation
58(1)
4.2.2 Inter-Die Versus Intra-Die Variation
58(1)
4.2.3 Correlated Versus Random Variation
59(1)
4.3 Sources of Random Process Variation
59(4)
4.3.1 Interconnect Variation
60(1)
4.3.2 Gate Variation
60(3)
4.4 Handling Process Variations
63(3)
4.4.1 Statistics Timing Analysis Methodologies
63(3)
4.5 Conclusions
66(5)
References
66(5)
Part II Impact of Process Variation on Low and High Levels Designs
5 Synchronous and Asynchronous NoC Design Under High Process Variation
71(16)
5.1 Introduction
71(1)
5.2 NoC Schemes
71(4)
5.2.1 Asynchronous Router
72(1)
5.2.2 Synchronous Router
73(1)
5.2.3 Network Interface Controller
74(1)
5.3 NoC Interconnection
75(5)
5.3.1 Interconnect Length in ASDs
75(4)
5.3.2 Clock Distribution in SYD
79(1)
5.4 Process Variation in NoC
80(5)
5.4.1 Delay Variation in NoC
81(2)
5.4.2 Throughput of NoC with Process Variation
83(1)
5.4.3 Leakage Power Variation
84(1)
5.5 Conclusions
85(2)
References
85(2)
6 Novel Routing Algorithm
87(14)
6.1 Introduction
87(1)
6.2 PDCR Algorithm
87(8)
6.2.1 Test Flit Description
88(1)
6.2.2 Modeling of DPV and Congestion
89(2)
6.2.3 PDCR Procedure
91(4)
6.3 Evaluation Metrics
95(1)
6.4 Conclusions
96(5)
References
96(5)
Part III Simulation Results and Future Work
7 Simulation Results
101(20)
7.1 Introduction
101(1)
7.2 Circuit-Level Simulation Results
101(12)
7.2.1 Nominal Delay
102(1)
7.2.2 Variation in NoC Design
102(7)
7.2.3 Throughput Variation
109(1)
7.2.4 Variation in Leakage Power
110(3)
7.3 Architecture-Level Simulation Results
113(8)
7.3.1 Impact of PV on the Performance of Routing Algorithms
113(2)
7.3.2 Simulation Results of PDCR
115(4)
References
119(2)
8 Conclusions
121(4)
8.1 Introduction
121(1)
8.2 Conclusions
121(4)
Appendix A 125(8)
Appendix B 133
Magdy Ali El-Moursy is an Associate Professor in the Microelectronics Department of the Electronics Research Institute, Cairo, Egypt and Staff Engineer at Design Creation and Synthesis Division of Mentor Graphics Corporation, Cairo, Egypt.
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