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E-raamat: Applications of Field-Programmable Gate Arrays in Scientific Research

(University of California, Santa Cruz, USA), (Fermi National Accelerator Laboratory, Batavia, Illinois, USA)
  • Formaat: 167 pages
  • Ilmumisaeg: 19-Apr-2016
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781040187494
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Applications of Field-Programmable Gate Arrays in Scientific ResearchSuurem pilt
  • Formaat: 167 pages
  • Ilmumisaeg: 19-Apr-2016
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781040187494
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Focusing on resource awareness in field-programmable gate array (FPGA) design, Applications of Field-Programmable Gate Arrays in Scientific Research covers the principle of FPGAs and their functionality. It explores a host of applications, ranging from small one-chip laboratory systems to large-scale applications in "big science."

The book first describes various FPGA resources, including logic elements, RAM, multipliers, microprocessors, and content-addressable memory. It then presents principles and methods for controlling resources, such as process sequencing, location constraints, and intellectual property cores. The remainder of the book illustrates examples of applications in high-energy physics, space, and radiobiology. Throughout the text, the authors remind designers to pay attention to resources at the planning, design, and implementation stages of an FPGA application, in order to reduce the use of limited silicon resources and thereby reduce system cost.

Supplying practical know-how on an array of FPGA application examples, this book provides an accessible overview of the use of FPGAs in data acquisition, signal processing, and transmission. It shows how FPGAs are employed in laboratory applications and how they are flexible, low-cost alternatives to commercial data acquisition systems.

Web Resource

A supporting website at http://scipp.ucsc.edu/~hartmut/FPGA offers more details on FPGA programming and usage. The site contains design elements of the case studies from the book, including VHDL code, detailed schematics of selected projects, photographs, and screen shots.
Preface ix
Acknowledgments xi
The authors xiii
Chapter 1 Introduction
1(4)
1.1 What is an FPGA?
1(1)
1.2 Digital and analog signal processing
1(1)
1.3 FPGA costs
1(2)
1.4 FPGA versus ASIC
3(2)
References
4(1)
Chapter 2 Understanding FPGA resources
5(6)
2.1 General-purpose resources
5(2)
2.1.1 Logic elements
5(1)
2.1.2 RAM blocks
6(1)
2.2 Special-purpose resources
7(1)
2.2.1 Multipliers
7(1)
2.2.2 Microprocessors
7(1)
2.2.3 High-speed serial transceivers
8(1)
2.3 The company-or family-specific resources
8(3)
2.3.1 Distributed RAM and shift registers
8(1)
2.3.2 MUX
8(1)
2.3.3 Content-addressable memory (CAM)
9(1)
References
9(2)
Chapter 3 Several principles and methods of resource usage control
11(10)
3.1 Reusing silicon resources by process sequencing
11(1)
3.2 Finding algorithms with less computation
12(1)
3.3 Using dedicated resources
13(1)
3.4 Minimizing supporting resources
14(2)
3.4.1 An example
14(1)
3.4.2 Remarks on tri-state buses
14(2)
3.5 Remaining in control of the compilers
16(2)
3.5.1 Monitoring compiler reports on resource usage and operating frequency
16(1)
3.5.2 Preventing useful logic from being synthesized away by the compiler
16(2)
3.5.3 Applying location constraints to help improve operating frequency
18(1)
3.6 Guideline on pipeline staging
18(1)
3.7 Using good libraries
19(2)
References
20(1)
Chapter 4 Examples of an FPGA in daily design jobs
21(22)
4.1 LED illumination
21(3)
4.1.1 LED rhythm control
21(2)
4.1.2 Variation of LED brightness
23(1)
4.1.3 Exponential drop of LED brightness
23(1)
4.2 Simple sequence control with counters
24(7)
4.2.1 Single-layer loops
25(2)
4.2.2 Multilayer loops
27(4)
4.3 Histogram booking
31(6)
4.3.1 Essential operations of histogram booking
31(2)
4.3.2 Histograms with fast booking capability
33(2)
4.3.3 Histograms with fast resetting capability
35(2)
4.4 Temperature digitization of TMP03/04 devices
37(1)
4.5 Silicon serial number (DS2401) readout
38(5)
References
41(2)
Chapter 5 The ADC + FPGA structure
43(16)
5.1 Preparing signals for the ADC
43(3)
5.1.1 Antialiasing low-pass filtering
43(1)
5.1.2 Dithering
44(2)
5.2 Topics on averages
46(4)
5.2.1 From sum to average
46(1)
5.2.2 Gain on measurement precision
46(1)
5.2.3 Weighted average
47(1)
5.2.4 Exponentially weighted average
48(2)
5.3 Simple digital filters
50(3)
5.3.1 Sliding sum and sliding average
51(1)
5.3.2 The CIC-1 and CIC-2 filters
52(1)
5.4 Simple data compression schemes
53(6)
5.4.1 Decimation and the decimation filters
53(2)
5.4.2 The Huffman coding scheme
55(1)
5.4.3 Noise sensitivity of Huffman coding
56(1)
References
57(2)
Chapter 6 Examples of FPGA in front-end electronics
59(38)
6.1 TDC in an FPGA based on multiple-phase clocks
59(3)
6.2 TDC in an FPGA based on delay chains
62(7)
6.2.1 Delay chains in an FPGA
63(1)
6.2.2 Automatic calibration
64(3)
6.2.3 The wave union TDC
67(2)
6.3 Common timing reference distribution
69(1)
6.3.1 Common start/stop signals and common burst
69(1)
6.3.2 The mean timing scheme of common time reference
70(1)
6.4 ADC implemented with an FPGA
70(4)
6.4.1 The single slope ADC
71(2)
6.4.2 The sigma-delta ADC
73(1)
6.5 DAC implemented with an FPGA
74(3)
6.5.1 Pulse width approach
74(1)
6.5.2 Pulse density approach
75(2)
6.6 Zero-suppression and time stamp assignment
77(1)
6.7 Pipeline versus FIFO
78(4)
6.8 Clock-command combined carrier coding (C5)
82(4)
6.8.1 The C5 pulses and pulse trains
82(1)
6.8.2 The decoder of C5 implemented in an FPGA
83(2)
6.8.3 Supporting front-end circuit via differential pairs
85(1)
6.9 Parasitic event building
86(2)
6.10 Digital phase follower
88(4)
6.11 Multichannel deserialization
92(5)
References
95(2)
Chapter 7 Examples of an FPGA in advanced trigger systems
97(18)
7.1 Trigger primitive creation
97(2)
7.2 Unrolling nested-loops, doublet finding
99(7)
7.2.1 Functional block arrays
100(2)
7.2.2 Content-addressable memory (CAM)
102(3)
7.2.3 Hash sorter
105(1)
7.3 Unrolling nested loops, triplet finding
106(4)
7.3.1 The Hough transform
108(2)
7.3.2 The tiny triplet finder (TTF)
110(1)
7.4 Track fitter
110(5)
References
114(1)
Chapter 8 Examples of an FPGA computation
115(10)
8.1 Pedestal and RMS
115(1)
8.2 Center of gravity method of pulse time calculation
116(2)
8.3 Lookup table usage
118(4)
8.3.1 Resource awareness in lookup table implementation
118(1)
8.3.2 An application example
119(3)
8.4 The enclosed loop microsequencer (ELMS)
122(3)
References
124(1)
Chapter 9 Radiation issues
125(6)
9.1 Radiation effects
125(1)
9.1.1 TID
125(1)
9.1.2 SEE effects
125(1)
9.2 FPGA applications with radiation issues
126(1)
9.2.1 Accelerator-based science
126(1)
9.2.2 Space
126(1)
9.3 SEE rates
127(1)
9.4 Special advantages and vulnerability of FPGAs in space
128(1)
9.5 Mitigation of SEU
129(2)
9.5.1 Triple modular redundant (TMR)
129(1)
9.5.2 Scrubbing
129(1)
9.5.3 Software mitigation: EDAC
129(1)
9.5.4 Partial reconfiguration
130(1)
References
130(1)
Chapter 10 Time-over threshold: The embedded particle-tracking silicon microscope (EPTSM)
131(8)
10.1 EPTSM system
131(2)
10.2 Time-over-threshold (TOT): analog ASIC PMFE
133(2)
10.3 Parallel-to-serial conversion
135(1)
10.4 FPGA function
135(4)
References
137(2)
Appendix: Acronyms 139(4)
Index 143
Hartmut F.-W. Sadrozinski is a research physicist and adjunct professor at the University of California, Santa Cruz. A senior fellow of the IEEE, Dr. Sadrozinski has been working on the application of silicon sensors and front-end electronics in elementary particle physics and astrophysics for over 30 years. He is currently involved in the use of silicon sensors to support hadron therapy. He earned his Ph.D. from the Massachusetts Institute of Technology.

Jinyuan Wu is an electronics engineer in the Particle Physics Division of Fermi National Accelerator Laboratory. Dr. Wu is a frequent lecturer at international workshops and IEEE conferences. He earned his Ph.D. in experimental high energy physics from Pennsylvania State University.
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