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Architecture and Modeling |
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Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks |
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3 | (12) |
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A Vector Caching Scheme for Streaming FPGA SpMV Accelerators |
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15 | (12) |
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Hierarchical Dynamic Power-Gating in FPGAs |
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27 | (14) |
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Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation |
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41 | (12) |
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ArchHDL: A Novel Hardware RTL Design Environment in C++ |
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53 | (12) |
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Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA |
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65 | (14) |
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Systems and Applications I |
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Preemptive Hardware Multitasking in ReconOS |
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79 | (12) |
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A Fully Parallel Particle Filter Architecture for FPGAs |
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91 | (12) |
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TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools |
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103 | (14) |
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Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures |
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117 | (12) |
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SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs |
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129 | (12) |
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Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties |
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141 | (12) |
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Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components |
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153 | (14) |
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Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays |
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167 | (12) |
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Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip |
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179 | (12) |
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Survey on Real-Time Network-on-Chip Architectures |
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191 | (14) |
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Cryptography Applications |
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205 | (12) |
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Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study |
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217 | (12) |
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Dual CLEFIA/AES Cipher Core on FPGA |
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229 | (14) |
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Systems and Applications II |
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An Efficient and Flexible FPGA Implementation of a Face Detection System |
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243 | (12) |
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A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context |
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255 | (12) |
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A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank |
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267 | (13) |
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The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs |
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280 | (13) |
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Extended Abstracts (Posters) |
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A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures |
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293 | (8) |
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Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA |
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301 | (10) |
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A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware |
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311 | (10) |
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Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures |
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321 | (10) |
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Efstathios Sotiriou-Xanthopoulos |
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Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects |
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331 | (8) |
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Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments |
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339 | (10) |
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DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems |
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349 | (8) |
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Acceleration of Data Streaming Classification using Reconfigurable Technology |
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357 | (8) |
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On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach |
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365 | (8) |
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Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform |
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373 | (10) |
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A Challenge of Portable and High-Speed FPGA Accelerator |
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383 | (10) |
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Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array |
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393 | (8) |
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Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture |
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401 | (10) |
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Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization |
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411 | (8) |
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DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost |
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419 | (8) |
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A Flexible Multilayer Perceptron Co-processor for FPGAs |
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427 | (8) |
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Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs |
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435 | (8) |
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Towards Performance Modeling of 3D Memory Integrated FPGA Architectures |
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443 | (8) |
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Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL |
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451 | (12) |
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Shinya Takamaeda-Yamazaki |
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Special Session 1 Funded R&D Running and Completed Projects (Invited Papers) |
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Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing |
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463 | (12) |
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SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms |
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475 | (12) |
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Marcos Aviles Rodrigalvarez |
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Hardware Task Scheduling for Partially Reconfigurable FPGAs |
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487 | (12) |
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SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring |
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499 | (14) |
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Special Session 2 Horizon 2020 Funded Projects (Invited Papers) |
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DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications |
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513 | (6) |
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Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective |
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519 | (12) |
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Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach |
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531 | (11) |
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COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator |
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542 | (13) |
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| Author Index |
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555 | |
Lisainfo e-raamatute kohta